A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction

Panigada, Andrea; Galton, I.

doi:10.1109/jssc.2009.2032637

Cited by 121 publications

(51 citation statements)

References 25 publications

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“…Each stage calibration time is about 2 12 ADC sampling periods, so the total calibration time is about 14 × 2 12 ADC sampling periods. The achieved performance for the pipelined ADC and the comparison with recently reported ADCs is shown in Table I using a figure of merit (FoM) defined by F oM = P ower 2 ENOB f S V DD as [4], where P ower, f S and V DD refer to the ADC power consumption, sampling frequency and supply voltage respectively and EN OB shows its effective number of bits. The simulated ADC shows the lowest FoM verifying the usefulness of the proposed calibration technique in design of high-speed and high-resolution pipelined ADCs.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Recently, a few digital calibration techniques that cancel the precision limitations of pipelined ADCs have been proposed [1,2,3,4]. In these methods, the errors are generally measured using a calibration signal where the precision of this signal in deep-submicron technologies is an important issue.…”

Section: Introductionmentioning

confidence: 99%

“…An accurate DAC calibrated with an additional calibration cycle is used in [1] to produce accurate calibration signals where in [2] with driving the mean square of 128 local errors across the input range to zero, they are measured using a medium-precision calibration signal. A high-precision on-chip DAC is used for 10-bit resolution in [3] and in [4] an accurate calibration signal produced with the DAC noise cancellation technique is used. Here, an efficient method is proposed which uses the lowest extra analog elements without the need for an accurate calibration signal.…”

Section: Introductionmentioning

confidence: 99%

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A novel digital calibration technique for pipelined ADCs

Moosazadeh

Yavari

2010

IEICE Electron. Express

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This paper presents a digital background calibration technique to correct the capacitors mismatch, gain error and gain nonlinearities of 1.5 bit/stage pipelined ADCs. The calibration technique uses a modified structure for the ADC stages, the skip-fill method and LMS algorithm and does not require any accurate calibration signal and any added analog circuitry; just some digital circuits are needed to fill the skipped samples and realize the LMS algorithm. Circuit level simulation results in a 90-nm CMOS technology are provided for a 12-bit 80-MS/s pipelined ADC to verify the effectiveness of the proposed calibration technique. Keywords: pipelined ADCs, capacitor mismatch, gain error, amplifier nonlinearity, digital background calibration, skip-fill method Classification: Integrated circuits References[1] C. Grace, P. J. Hurst, and S. H. Lewis, "A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration," IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1038-1046

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A novel digital calibration technique for pipelined ADCs

Moosazadeh

Yavari

2010

IEICE Electron. Express

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“…A common approach is to employ low-gain and/or non-settling op-amps, and digitally calibrate the resulting nonlinearity [2][3][4][5]. In order to track the power supply voltage and temperature, the calibration in general must run continuously in the background, which can consume significant power.…”

Section: Introductionmentioning

confidence: 99%

15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers

Boo

Boning

Lee

2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

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The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unitygain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12b pipelined ADC is implemented in 65nm CMOS that achieves 67.0dB SNDR at 250MS/s and consumes 49.7mW of power from a 1.2V power supply.

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“…1 The steps causing discontinuities in the A/D converter's stage transfer functions can be analyzed, minimized or corrected with a wide variety of calibration techniques. [2][3][4][5][6][7] The mismatch and error attached to each step can either be averaged out, or their magnitude can be measured and corrected. In general, most of the debugging and calibration methods require that a reference signal is available in the digital domain, this being the signal that the actual stage output of the A/D converter is compared with.…”

Section: Introductionmentioning

confidence: 99%

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters

Zjajo¹,

Barragán²,

Gyvez³

2012

Journal of Low Power Electronics

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This paper reports a novel approach for calibration of multi-step A/D converters based on the steepest-descent estimation method. The calibration procedure is enhanced with dedicated embedded sensors, which register on-chip process parameter and temperature variations. Additionally, to guide the verification process with the information obtained through process monitoring, two efficient algorithms based on an expectation-maximization method and adjusted support vector machine classifier, respectively, are proposed. The algorithms are evaluated on a prototype 12 bits A/D converter fabricated in standard single poly, six metal 90 nm CMOS.

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A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction

Cited by 121 publications

References 25 publications

A novel digital calibration technique for pipelined ADCs

A novel digital calibration technique for pipelined ADCs

15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters

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