This brief demonstrates a new adaptive digital predistortion architecture particularly suited to mobile handset applications. The central idea is to build a lookup table (LUT) that directly captures the static compressive nonlinearity of the power amplifier (PA) and then insert this LUT into the feedback path of a ΔΣ modulator. The oversampled ΔΣ modulator automatically performs both the inversion of the PA nonlinearity and the interpolation between LUT entries, permitting complex modulation strategies to be handled with an absolute minimum of LUT entries and with a dramatically simplified computational structure. The advantages of this architecture over previous methods include:
1) there is no need to explicitly invert the PA nonlinearity, reducing the complexity for the system designer; 2) the LUT training is done with an open-loop method, improving the training speed; 3) there is no need to explicitly employ numerical interpolation between LUT entries; and 4) digital-to-analog converter (DAC)nonlinearity is incorporated into the predistortion, allowing fast low-resolution DACs to be used in the final system. We built a proof-of-concept prototype for a 900-MHz, 27-dBm PA transmitting a 16-ary quadrature amplitude modulation (16-QAM) signal with a bandwidth of 3.4 MHz. The predistortion system reduced out-of-band distortion products by 10 dB and improved the error vector magnitude from 3.5% to 2.0%.
The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unitygain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12b pipelined ADC is implemented in 65nm CMOS that achieves 67.0dB SNDR at 250MS/s and consumes 49.7mW of power from a 1.2V power supply.
The virtual ground reference buffer (VGRB) technique is introduced as a means to improve the performance of switched-capacitor circuits. The technique enhances the performance by improving the feedback factor of the op-amp without affecting the signal gain. The bootstrapping action of the level-shifting buffers relaxes key op-amp performance requirements including unitygain bandwidth, noise, open-loop gain and offset compared with conventional circuits. This reduces the design complexity and the power consumption of op-amp based circuits. Based on this technique, a 12b pipelined ADC is implemented in 65nm CMOS that achieves 67.0dB SNDR at 250MS/s and consumes 49.7mW of power from a 1.2V power supply.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.