A 130-$\mu$W, 64-Channel Neural Spike-Sorting DSP Chip

Karkare, Vaibhav; Gibson, Sarah; Marković, Dejan

doi:10.1109/jssc.2011.2116410

Cited by 91 publications

(52 citation statements)

References 16 publications

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“…The measured results have shown compression performance that is on the same order of magnitude as previous feature extraction systems [3]- [6] without requiring any decision making at the sensor node, while the energy-efficiency and power cost of the system is on par with or better than a custom feature extraction ASIC [7]. However, since CS is performing data compression rather than any decision making, it is more appropriate to compare it to other compression/source coding schemes.…”

Section: Compression Performance and Costmentioning

confidence: 88%

“…For a pseudo-random bit sequence (PRBS) of samples, the resulting noise accumulated during an integration window is times the output noise of a single sample, where the output noise density is filtered by the gain and effective noise bandwidth of an integrator with th the integration period. The total integrated output noise needs to be less than the quantization noise of the ADC leading to 7 (11)…”

Section: Mixermentioning

confidence: 99%

“…Existing strategies for implementing integrated data compression or filtering solutions under these constraints largely revolve around detecting and extracting specific signal data [3]- [7]. However, the filtered data often contains limited information.…”

Section: Introductionmentioning

confidence: 99%

“…Even when the event detection is used to trigger a full signal capture [4], the system is susceptible to missing events entirely if detection thresholds are not properly set. Meanwhile, feature extraction approaches require training, are usually signal specific and typically provide only macro level decisions based on the original signals [6], [7]. For these signal processing strategies, there is a tradeoff between data reduction, robustness, implementation cost, and the granularity of information captured.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors

Chen

Chandrakasan

Stojanović

2012

IEEE J. Solid-State Circuits

336

222

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Abstract-This work introduces the use of compressed sensing (CS) algorithms for data compression in wireless sensors to address the energy and telemetry bandwidth constraints common to wireless sensor nodes. Circuit models of both analog and digital implementations of the CS system are presented that enable analysis of the power/performance costs associated with the design space for any potential CS application, including analog-to-information converters (AIC). Results of the analysis show that a digital implementation is significantly more energy-efficient for the wireless sensor space where signals require high gain and medium to high resolutions. The resulting circuit architecture is implemented in a 90 nm CMOS process. Measured power results correlate well with the circuit models, and the test system demonstrates continuous, on-the-fly data processing, resulting in more than an order of magnitude compression for electroencephalography (EEG) signals while consuming only 1.9 W at 0.6 V for sub-20 kS/s sampling rates. The design and measurement of the proposed architecture is presented in the context of medical sensors, however the tools and insights are generally applicable to any sparse data acquisition.

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Section: Compression Performance and Costmentioning

confidence: 88%

Section: Mixermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors

Chen

Chandrakasan

Stojanović

2012

IEEE J. Solid-State Circuits

336

222

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“…Until recently, the consensus was to implement the classification process after transmission because of its high complexity. For this there are a num- (Karkare et al, 2011) 2011 NEO DD -64 2.03 0.09 0.06 (Chen et al, 2012) 2012 NEO DWT/PCA k-means 128 0.68 0.09 0.07 * (Kamboh and Mason, 2012) 2012 DT ZCF Mahalanobis ---- (Karkare et al, 2013) 2013 Abs PP modified k-means 16 4.68 0.065 0.07 * (Saeed and Kamboh, 2013) 2013 NEO ZCF MCK classifier ----*This paper shows the potential of hardware implementation.…”

Section: Introductionmentioning

confidence: 99%

Hierarchical Adaptive Means (HAM) clustering for hardware-efficient, unsupervised and real-time spike sorting

Paraskevopoulou

Eftekhar

et al. 2014

Journal of Neuroscience Methods

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This work presents a novel unsupervised algorithm for real-time adaptive clustering of neural spike data (spike sorting). The proposed Hierarchical Adaptive Means (HAM) clustering method combines centroid-based clustering with hierarchical cluster connectivity to classify incoming spikes using groups of clusters. It is described how the proposed method can adaptively track the incoming spike data without requiring any past history, iteration or training and autonomously determines the number of spike classes. Its performance (classification accuracy) has been tested using multiple datasets (both simulated and recorded) achieving a near-identical accuracy compared to k-means (using 10-iterations and provided with the number of spike classes). Also, its robustness in applying to different feature extraction methods has been demonstrated by achieving classification accuracies above 80% across multiple datasets. Last but crucially, its low complexity, that has been quantified through both memory and computation requirements makes this method hugely attractive for future hardware implementation.

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