A 128 × 128 Current-Mode Ultra-High Frame Rate ISFET Array With In-Pixel Calibration for Real-Time Ion Imaging

Abstract

An ultra-high frame rate and high spatial resolution ion-sensing Lab-on-Chip platform using a 128 × 128 CMOS ISFET array is presented. Current mode operation is employed to facilitate high-speed operation, with the ISFET sensors biased in the triode region to provide a linear response. Sensing pixels include a reset switch to allow in-pixel calibration for nonidealities such as offset, trapped charge and drift by periodically resetting the floating gate of the ISFET sensor. Current mode row-parallel signal processing is applied throughout the readout pipeline including auto-zeroing circuits for the removal of fixed pattern noise. The 128 readout signals are multiplexed to eight high-sample-rate on-chip current mode ADCs followed by an off-chip PCIe-based readout system on a FPGA with a latency of 0.15 s. Designed in a 0.35 µm CMOS process, the complete system-on-chip occupies an area of 2.6 × 2.2 mm 2 with a pixel size of 18 × 12.5 µm 2 and the whole system achieves a frame rate of 3000 fps which is the highest reported in the literature for ISFET arrays. The platform is demonstrated in the application of real-time ion-imaging through the high-speed visualization of sodium hydroxide (NaOH) diffusion in water at 60 fps on screen in addition to slow-motion playback of ion-dynamics recorded at 3000 fps. Index Terms-ISFET, ultra-high frame rate, linearity conversion, current mode, in-pixel calibration. Junming Zeng (S'17) received the Bachelor degree with first class honors in Electronic Engineering from the University of Southampton, UK in 2016, and the Master degree with Distinction in Analogue and Digital Integrated Circuit Design from Imperial College London, UK in 2017. He is currently a PhD student with Centre for Bio-Inspired Technology, Department of Electrical and Electronic Engineering, Imperial College London UK. His research interests include Analogue and Mixed Signal IC design and digital system design for biomedical applications. Specifically, he is now working on designing a CMOS Labon-Chip ultra-high speed ion imaging platform. He is the recipient of the Department PhD Scholarship from Imperial College London, and the awardee of the Best Student Paper Award 1st Prize at ISCAS 2018. Lei Kuang received the B.Sc. degree in Industrial electronics and control engineering from the Liverpool John Moores University, Liverpool, UK in 2016 and the M.Sc. degree in embedded systems from the University of Southampton, Southampton, UK in 2017. Then, he spent one year working as an embedded system design engineer in China's IC industry for SoC IP design and FPGA development. He is currently working toward his second M.Sc. degree in analog and digital integrated circuit design at Imperial College London, London, UK. His interests include high-speed and low-power digital system design, image processing and algorithm acceleration on FPGAs.

A Digital ISFET Sensor with In-Pixel ADC

“…Since its first implementation in standard CMOS technology back in 1999 [9], ISFET have looked for inspiration in fields with shared requirements and challenges, such as CMOS imagers, leading to a fruitful innovation transfer. Examples of this inspiration are the implementation of an APS-inspired architecture [10] or the recent trend towards ultra-high frame rate chemical imagers [11]. Furthermore, ISFET application requirements are driving the in-pixel integration of multiple sensing modalities [12], [13], as well as the incorporation of computational capabilities to the sensing platform that provide processing and learning functionalities [14], [15].…”

A 1000fps Programmable Gain CMOS ISFET SoC with Array-Level Offset Compensation for Real Time Ion Imaging

“…(2) Sensitivity -to maximise the surface intrinsic sensitivity as well as maximising the effective sensitivity in circuits through amplification [11], [12]. (3) Readout Speed -to boost the sampling rate of the ISFET in order to monitor high frequency ion interactions [13], [14]. (4) Spatial resolution -scaling the size of the array [15].…”

A USB 3.0 High Speed Digital Readout System with Dynamic Frame Rate Processing for ISFET Lab-on-Chip Platforms

“…Owing to its capability of fabrication in unmodified CMOS technologies, an array with a large scale of sensors can be integrated onto a mm-sized chip. As a result, recent technologies have enabled the monolithic integration of high spatial-temporal resolution ISFET arrays with high-speed processing circuits, forming a System-on-Chip for monitoring ion diffusion at a frame rate higher than 1000 fps [4], [5]. Meanwhile, existing off-chip readout platforms based on microcontrollers (MCU) witness a limitation on their readout speeds, where a typical data rate higher than 100 Mbps becomes a challenge.…”

“…As a result, a highspeed interface between the FPGA and the PC is required to provide real-time and long-term streaming. Improved readout systems proposed in [4], [8] consist of high-throughput serial ports such as Ethernet and PCIe. The current state-of-the art is able to process long-term and real-time data acquisition at a bit rate of 491.52 Mbps [9].…”