A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET

Erett, Marc; Carey, Declan; Hudner, James; Casey, Ronan; Geary, Kevin; Neto, Pedro; Raj, Mayank; McLeod, Scott; Zhang, Hongtao; Roldan, Arianne; Zhao, Hongyuan; Chiang, Po-Jui; Zhao, Huandong; Tan, KeeHian; Frans, Yohan; Chang, Ken

doi:10.1109/isscc.2018.8310290

Cited by 21 publications

(5 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Moreover, the clock forwarding scheme requires additional pad resources. The work from Shekhar et al [26] addresses these problems; however, this design is still a stand-alone system like the ones in [21], [23], [27] and ignores the essential functionality required by actual microcontrollers. On the other hand, our design meets all the requirements, such as the tight power envelope, limited number of pads, and system integration.…”

Section: Comparison To Other Short Reach Linksmentioning

confidence: 99%

“…While the other links achieve higher bandwidth and energy-efficiency than ours, they are missing the option to be integrated into actual microcontrollers. Indeed, the works from [23], [25], [27] are not suitable for low power applications as their total power consumption is much higher than the power envelope of an IoT edge devices (10mW). Also, the work in [21] does not consider power overhead imposed by extra voltage sources.…”

Section: Comparison To Other Short Reach Linksmentioning

confidence: 99%

See 1 more Smart Citation

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

Okuhara

Elnaqib

Dazzi

et al. 2021

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

The increasing complexity of Internet-of-Things (IoT) applications and near-sensor processing algorithms is pushing the computational power of low-power, battery-operated endnode systems. This trend also reveals growing demands for highspeed and energy-efficient inter-chip communications to manage the increasing amount of data coming from off-chip sensors and memories. While traditional micro-controller interfaces such as SPIs cannot cope with tight energy and large bandwidth requirements, low-voltage swing transceivers can tackle this challenge thanks to their capability to achieve several Gbps of the communication speed at milliwatt power levels. However, recent research on high-speed serial links focused on high-performance systems, with a power consumption significantly larger than the one of low-power IoT end-nodes, or on stand-alone designs not integrated at a system level. This paper presents a low-swing transceiver for the energy-efficient and low power chip-to-chip communication fully integrated within an IoT end-node Systemon-Chip, fabricated in CMOS 65nm technology. The transceiver can be easily controlled via a software interface; thus, we can consider realistic scenarios for the data communication, which cannot be assessed in stand-alone prototypes. Chip measurements show that the transceiver achieves 8.46x higher energy efficiency at 15.9x higher performance than a traditional microcontroller interface such as a single-SPI.

show abstract

Section: Comparison To Other Short Reach Linksmentioning

confidence: 99%

Section: Comparison To Other Short Reach Linksmentioning

confidence: 99%

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

Okuhara

Elnaqib

Dazzi

et al. 2021

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…Prior work has shown multiple chiplet-based architectures for various applications such as DNN acceleration, general purpose system-on-chips (SoCs), and recommendation systems [3,7,13,22,35,42,45], which present different on-package signaling techniques and associated circuitries. We limit the description of these works to three for brevity.…”

Section: Chiplet-based Architecturesmentioning

confidence: 99%

SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks

Krishnan,

Mandal,

Pannala

et al. 2021

Preprint

View full text Add to dashboard Cite

In-memory computing (IMC) on a monolithic chip for deep learning faces dramatic challenges on area, yield, and on-chip interconnection cost due to the ever-increasing model sizes. 2.5D integration or chiplet-based architectures interconnect multiple small chips (i.e., chiplets) to form a large computing system, presenting a feasible solution beyond a monolithic IMC architecture to accelerate large deep learning models. This paper presents a new benchmarking simulator, SIAM, to evaluate the performance of chiplet-based IMC architectures and explore the potential of such a paradigm shift in IMC architecture design. SIAM integrates device, circuit, architecture, network-on-chip (NoC), network-on-package (NoP), and DRAM access models to realize an end-to-end system. SIAM is scalable in its support of a wide range of deep neural networks (DNNs), customizable to various network structures and configurations, and capable of efficient design space exploration. We demonstrate the flexibility, scalability, and simulation speed of SIAM by benchmarking different state-of-the-art DNNs with CIFAR-10, CIFAR-100, and ImageNet datasets. We further calibrate the simulation results with a published silicon result, SIMBA. The chiplet-based IMC architecture obtained through SIAM shows 130× and 72× improvement in energy-efficiency for ResNet-50 on the ImageNet dataset compared to Nvidia V100 and T4 GPUs. CCS Concepts: • Hardware → Analysis and Design of Emerging Devices and Systems; On-chip Resource Management; Emerging Architectures; Interconnect; System-on-a-chip.

show abstract

“…Two 56-Gb/s NRZ transceivers and a 64-Gb/s PAM4 transceiver proposed in previous works [6][7][8] can be applied for high-speed die-to-die links. However, their energy efficiency falls between 4 and 6 pJ/bit, which is comparatively low.…”

Section: Introductionmentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

show abstract

A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET

Cited by 21 publications

References 3 publications

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Contact Info

Product

Resources

About