2018 IEEE International Solid - State Circuits Conference - (ISSCC) 2018
DOI: 10.1109/isscc.2018.8310290
|View full text |Cite
|
Sign up to set email alerts
|

A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
5
0

Year Published

2019
2019
2023
2023

Publication Types

Select...
5
2
1

Relationship

0
8

Authors

Journals

citations
Cited by 21 publications
(5 citation statements)
references
References 3 publications
0
5
0
Order By: Relevance
“…Moreover, the clock forwarding scheme requires additional pad resources. The work from Shekhar et al [26] addresses these problems; however, this design is still a stand-alone system like the ones in [21], [23], [27] and ignores the essential functionality required by actual microcontrollers. On the other hand, our design meets all the requirements, such as the tight power envelope, limited number of pads, and system integration.…”
Section: Comparison To Other Short Reach Linksmentioning
confidence: 99%
See 1 more Smart Citation
“…Moreover, the clock forwarding scheme requires additional pad resources. The work from Shekhar et al [26] addresses these problems; however, this design is still a stand-alone system like the ones in [21], [23], [27] and ignores the essential functionality required by actual microcontrollers. On the other hand, our design meets all the requirements, such as the tight power envelope, limited number of pads, and system integration.…”
Section: Comparison To Other Short Reach Linksmentioning
confidence: 99%
“…While the other links achieve higher bandwidth and energy-efficiency than ours, they are missing the option to be integrated into actual microcontrollers. Indeed, the works from [23], [25], [27] are not suitable for low power applications as their total power consumption is much higher than the power envelope of an IoT edge devices (10mW). Also, the work in [21] does not consider power overhead imposed by extra voltage sources.…”
Section: Comparison To Other Short Reach Linksmentioning
confidence: 99%
“…Prior work has shown multiple chiplet-based architectures for various applications such as DNN acceleration, general purpose system-on-chips (SoCs), and recommendation systems [3,7,13,22,35,42,45], which present different on-package signaling techniques and associated circuitries. We limit the description of these works to three for brevity.…”
Section: Chiplet-based Architecturesmentioning
confidence: 99%
“…Two 56-Gb/s NRZ transceivers and a 64-Gb/s PAM4 transceiver proposed in previous works [6][7][8] can be applied for high-speed die-to-die links. However, their energy efficiency falls between 4 and 6 pJ/bit, which is comparatively low.…”
Section: Introductionmentioning
confidence: 99%