A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed

Imamiya, K.; Nakamura, Hiroshi; Himeno, T.; Yarnamura, T.; Ikehashi, Tamio; Takeuchi, Ken; Kanda, K.; Hosono, Koji; Futatsuyama, T.; Kawai, K.; Shirota, R.; Arai, Norihisa; Arai, F.; Hatakeyama, K.; Hazama, H.; Saito, Masato; Meguro, H.; Conley, Ken; Quader, K.; Chen, J.J.

doi:10.1109/jssc.2002.802355

Cited by 22 publications

(12 citation statements)

References 7 publications

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“…Figure 2(a) shows the concepts of the conventional cache program [7]. In the beginning of the cache program, the data from the first page are loaded to the cache buffer (CB), which is referred to as the "Load" operation in the figure.…”

Section: Conventional Cache Program Methodsmentioning

confidence: 99%

“…In the SSD operation, since peak ICC increases as N increases, the maximum N is restricted by an ICC constraint [1]. One of the most well-known strategies for improving Performance_NAND is to use a cache program operation [7]. Here, since ICC increases with ICC4W, a large N gives rise to a large peak ICC [7].…”

Section: Program Cache Busy Time Control Methods For Reducing Peak Curmentioning

confidence: 99%

“…Here, since ICC increases with ICC4W, a large N gives rise to a large peak ICC [7]. The proposed program Cache Busy Time (tPCBSY) control method can effectively reduce the peak ICC of a cache program without restricting N [7].…”

Section: Program Cache Busy Time Control Methods For Reducing Peak Curmentioning

confidence: 99%

“…One of the most well-known strategies for improving Performance_NAND is to use a cache program operation [7]. The proposed program Cache Busy Time (tPCBSY) control method can effectively reduce the peak ICC of a cache program without restricting N [7]. The proposed program Cache Busy Time (tPCBSY) control method can effectively reduce the peak ICC of a cache program without restricting N [7].…”

Section: Introductionmentioning

confidence: 99%

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Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications

Park

Kim

Cho

et al. 2014

ETRI J

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In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory — namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit‐line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid‐state drive.

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Section: Conventional Cache Program Methodsmentioning

confidence: 99%

Section: Program Cache Busy Time Control Methods For Reducing Peak Curmentioning

confidence: 99%

Section: Program Cache Busy Time Control Methods For Reducing Peak Curmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications

Park

Kim

Cho

et al. 2014

ETRI J

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show abstract

“…NAND Flash achieves high program speed of 10MB/s [1] among all Flash memories, which is 1/10 to that of HDD's, and conventional NOR Flash does much less. We proposed new program mechanism, B4-HE, and confirmed its high speed and highly efficient program properties, which showed the possibility to realize 100MB/s programmability [2].…”

Section: Introductionmentioning

confidence: 99%

A 1.8V 4Mb Floating-Gate NOR Type B4-Flash Test Chip for 100MB/s Programming Speed

Mihara¹,

Kawajiri²,

Kobayashi³

et al. 2007

2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop

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A 1.8V 4Mb floating-gate Flash test chip utilizing Back Bias assisted Band-to-Band tunneling induced Hot Electron (B4-HE) injection mechanism (B4-Flash) has been fabricated. Double Source Line Architecture (DSLA) and Selective Verifying Method (SVM), applied to NOR arrayed B4-Flash enables to achieve 100MB/s programming speed. The MLC capability of B4-Flash memory is also shown by realizing three levels of programmed Vth distribution with 0.8V width.

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NAND design for testability and testing

Silvagni¹

2010

Inside NAND Flash Memories

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A 125-mm/sup 2/ 1-Gb NAND flash memory with 10-MByte/s program speed

Cited by 22 publications

References 7 publications

Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications

Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications

A 1.8V 4Mb Floating-Gate NOR Type B4-Flash Test Chip for 100MB/s Programming Speed

NAND design for testability and testing

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