A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

Ebuchi, Tsuyoshi; Komatsu, Yoshihide; Okamoto, Tatsuo; Arima, Yutaka; Yamada, Yuji; Sogawa, K.; Okamoto, K.; Matsukawa, Takashi; Hirata, Tetsuyasu; Dosho, Shiro; Yoshikawa, Takefumi

doi:10.1109/jssc.2009.2013756

Cited by 32 publications

(7 citation statements)

References 7 publications

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“…The counter content , after one half-period of D0 will be (11) Afterward, the DCDL is driven with and the down-counting is selected. After another one-half period of D0, the counter content becomes (12) By substituting (10) in this expression we have (13) where (14) In practice, is chosen equal to a power of two, so that the value of is obtained as a shift of the counter value. From (13), yields the ratio with an absolute error: (15) The measurement time is (16) By reducing we improve both the measurement error and the measurement time, but we increase also the frequency of the ring oscillator.…”

Section: B Measurement Unitmentioning

confidence: 99%

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A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

De¹,

Romani

Petra³

et al. 2010

IEEE J. Solid-State Circuits

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Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range, with a predefined modulation profile.We present the implementation of an all-digital spread spectrum clock generator. The circuit is realized by using a design flow completely based on standard cells and is able to perform clock spreading with an arbitrary modulation profile and a modulation frequency up to 5 MHz. The circuit uses two digitally controlled delay lines driven by a digital modulator to synthesize the output waveform. A replica delay line is employed in a real-time measurement circuit to track process, voltage and temperature variations.A chip has been implemented in a 65 nm CMOS technology. The chip is able to generate signals up to 1.27 GHz. The measured peak level reduction of the clock spectrum, at 750 MHz output frequency, is 20.5 dB with a 6% modulation depth. The power dissipation is 44 mW @ 1.27 GHz.Index Terms-Clock synthesis, digitally controlled delay line, EMI reduction, spread-spectrum clock generator (SSCG).

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Section: B Measurement Unitmentioning

confidence: 99%

“…Several techniques have been proposed, including direct modulation of the VCO [9], [10], two-point modulation [11] and the use of fractional-N modulation [12]- [22]. The use of a delay locked loop followed by a phase selector is investigated in [23].…”

Section: Introductionmentioning

confidence: 99%

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

De¹,

Romani

Petra³

et al. 2010

IEEE J. Solid-State Circuits

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“…3 Transmitter core design The transmitter contains 24 data Tx channels, an adaptive-bandwidth spread spectrum clock generator (AB-SSCG) [13], a clock tree (CK tree), and a bias generator (APNBG). N-bit parallel data is multiplexed to differential serial data.…”

Section: Concept Of Dual Extensionmentioning

confidence: 99%

An ultra-wide range (0.01–240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator

Ebuchi

Toshikawa

Watanabe

et al. 2018

IEICE Electron. Express

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This paper proposes an ultra-wide range transmitter with a latched AC-coupled driver (LACD) and a dummy data transient generator (DDTG). The LACD expands the low-frequency range by preventing the capacitor discharge issue of the high-speed AC-coupled driver and the DDTG enhances the high-frequency range by generating a dummy transient pattern to stabilize the power node fluctuation induced by the dense and sparse pattern dependency in the case of coding-less application. A 24-channel test chip designed with 40-nm CMOS technology achieved an ultrawide frequency range (0.01-10 Gbps/channel) and ultra-wide bandwidth from 0.01 Gbps (0.01 Gbps × 1 channel) to 240 Gbps (10 Gbs × 24 channels) and a high area efficiency (0.0027 mm 2 /Gbps/channel). At the data rates of 5 and 10 Gbps, the jitters with DDTG were 50% lower than attained without DDTG.

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“…The SSCG has a frequency deviation from 610 Hz to 1.6 GHz (0-80%) and modulation frequency range from 2.38 Hz to 100 kHz. The minimum frequency resolution is 610 Hz (f REF /2 15 ). Most of the SSCG standards for high speed seriallink demand a modulation frequency range from 30 to 33 kHz and a frequency deviation of -0.5%.…”

Section: A Programmable Lfmmentioning

confidence: 99%

“…However, the nonlinear varactor characteristic of an LC-VCO or a nonlinear current mirroring factor of a ring-based oscillator causes nonlinear relation between the frequency and control signal, resulting in an irregular frequency modulation. Therefore, an additional compensation circuit is required to enhance the modulation linearity [15]. A closed-loop control technique adjusts the frequency-division ratio (FDR) of a PLL periodically with a delta-sigma modulator (DSM) to generate the SSC [13]- [17].…”

Section: Introductionmentioning

confidence: 99%

A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices

Ryu

Park

Sung

et al. 2015

IEEE Trans. Electromagn. Compat.

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This paper presents a fractional-N phase-locked loop based spread spectrum clock generator (SSCG) using a programmable linear frequency modulator. The SSCG provides a programmable frequency deviation and modulation frequency regardless of its operating frequency. The ranges of frequency-deviation ratio and modulation frequency are 0-80% and 0-100 kHz with 610 Hz step resolution. The proposed SSCG successfully support five serial-link standards by using a single SSCG, and can be applied to various switching circuits such as class-D power amplifiers or switching power converters. The EMI reduction was measured to be 10.24-13.94 dB under 100-kHz resolution bandwidth. The proposed SSCG was fabricated using a 0.13-μm CMOS process with an active area of 0.11 mm 2 , while consuming an overall power of 6.28 mW at 1 GHz. Index Terms-EMI reduction, frequency modulation, phase locked loop (PLL), spread spectrum clock generator (SSCG). 0018-9375Sangyong Park (S'11) received the B.S. and M.S. degrees from the School of Electrical Engineering, Chung-Ang University, Seoul, South Korea, in 2011 and 2013, respectively. He is currently working toward the Ph.D. degree at the School of Electrical Engineering, Chung-Ang University.His research interests include delta-sigma modulators, the design of linear regulators for wireless communication, and clock and data recovery circuits for high speed communication using CMOS technology.Eun-Taek Sung (S'14) received the B.S. degree from the School of Electrical Engineering, Chung-Ang University, Seoul, South Korea, in 2014. He is currently working toward the M.S. degree at the School of Electrical Engineering, Chung-Ang University.His research interests include the design of lowpower and energy-efficient sensor interfaces, data converters, and high performance clock generators for wireless sensor networks.Seung-Gi Lee received the B.S. degree from the School of Electrical Engineering, Chung-Ang University, Seoul, South Korea, in 2015. He is currently working toward the M.S. degree at the School of Electrical Engineering, Chung-Ang University.His research interests include the design of linear regulators, high power amplifier, and CMOS RF transceiver design for the wireless communication. DonghyunBaek (S'98-M'07-SM'13) received the B.S., M.S., and Ph.D. degrees from the

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A 125–1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

Cited by 32 publications

References 7 publications

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS

An ultra-wide range (0.01–240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator

A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices

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