A 120nm low power asynchronous ADC

Allier, E.; Goulier, J.; Sicard, G.; Dezzani, A.; André, E.; Renaudin, M.

doi:10.1145/1077603.1077619

Cited by 14 publications

(5 citation statements)

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“…Note that associating a timestamp with the output would only require an additional counter, which would not require significant additional power [2] (approximately 15 µW). However, the data presented by Renaudin [1] is a result of measurements, and all the data presented in this paper is a result of simulations and will be confirmed after the LCF-ADC is fabricated.…”

supporting

confidence: 58%

“…A comparison of using synchronous and asynchronous methods [13] for ADCs studied the effect of using asynchronous logic in ADC implementations; previously, a flash-type ADC was implemented using micropipelines [12]. Recently, several schemes utilizing level-crossing were developed [1,2]. However, the goal of those designs is signal reconstruction.…”

Section: Introductionmentioning

confidence: 99%

“…Our ADC simulations were performed with varying signal bandwidth (up to 5 MHz) with 4 bits of hardware resolution as well, and we use significantly less power than the A-ADC over the entire range. The A-ADC, however, was designed in a different fabrication technology (0.25 µm); however, a more recent version of the same architecture in 0.12 µm CMOS shows a maximum bandwidth of 160 kHz, and a power consumption of 180 µW, even though their results correspond to a better fabrication technology [1]. An implementation similar to Renaudin's A-ADC was presented by Shepard et al [14,15]; the power consumption was in the milli-Watt range -higher then in Renaudin's A-ADC.…”

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confidence: 99%

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A Level-Crossing Flash Asynchronous Analog-to-Digital Converter

Akopyan

Manohar

Apsel

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)

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Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-to-digital converter (ADC) to process analog signals from the physical world. We describe a new topology for an asynchronous analog-to-digital converter, dubbed LCF-ADC, that has several major advantages over previously-designed ADCs, including reduced energy consumption and/or a simplification of the analog circuits required for its implementation.In this paper we describe the design of the LCF-ADC architecture, and present simulation results that show low power consumption. We discuss both theoretical considerations that determine the performance of our ADC as well as a proposed implementation. Comparisons with previously designed asynchronous analog-to-digital converters show the benefits of the LCF-ADC architecture. In 180 nm CMOS, our ADC is expected to consume 43 µW at 160 kHz, and 438 µW at 5 MHz.

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confidence: 58%

Section: Introductionmentioning

confidence: 99%

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confidence: 99%

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A Level-Crossing Flash Asynchronous Analog-to-Digital Converter

Akopyan

Manohar

Apsel

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)

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“…There is much ongoing work on CT-ADCs and CT-DACs [2], [3], [30], [36]. Also, a few CT-DSP silicon prototypes have been fabricated in domains like audio [24], [33] and RF [14], showing significant promise.…”

Section: B Prior Work: Ct Dsps and Adaptive Delay Linesmentioning

confidence: 99%

Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity

Vezyrtzis

Tsividis

Nowick

2015

IEEE Trans. VLSI Syst.

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A calibrated delay line is a key component in many modern digital systems. Traditionally, these lines are designed as real-time pipelines with static granularity, fine enough to handle a worst case input rate. However, due to their rigid structure, they have suboptimal energy for low-and varyingrate input streams. We introduce a complete methodology for designing reconfigurable delay lines that dynamically adapt their granularity to actual input traffic, on-the-fly, without stalling or disturbing normal operation. Two or more modes can be used, with different granularities to handle different traffic densities. During sparser traffic, the system is reconfigured to the proper coarser-grain mode, thereby reducing total energy, and it reverts to fine-grain mode during denser traffic. In each case, overall delay is preserved. This strategy is especially beneficial for applications where input traffic is highly varied. The particular focus of this paper is one promising domain, continuous-time digital signal processors (CT DSPs), a new class of processors targeting low-energy applications. The proposed system includes two lightweight asynchronous control blocks: a digital controller to continuously monitor input traffic, and a micropipeline to dynamically reconfigure the entire delay line. Design approaches for bimodal and trimodal adaptive lines are presented, which are then implemented in a 0.13-µm IBM CMOS technology. Simulations for these delay lines demonstrate savings in overall dynamic power up to 45.5% and 71.1%, respectively, when compared with a nonadaptive design, with only minimal area overhead (1.5% and 3%, respectively, for a targeted configuration). Using extensions to more configuration modes, further power reductions can be achieved. While results are presented for CT DSPs, significant benefits are also expected in many other domains, where the delay lines are used.Index Terms-Asynchronous systems, delay line, digital design, digital signal processor (DSP). 1063-8210

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“…8.78 [201,202] generates a new digital output code at each time moment an amplitude quantization level is passed. In this process rounding errors occurred, that were labeled quantization errors.…”

Section: Level-crossing Analog-to-digital Conversionmentioning

confidence: 99%

Analog-to-Digital Conversion

Pelgrom

2010

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A 120nm low power asynchronous ADC

Cited by 14 publications

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A Level-Crossing Flash Asynchronous Analog-to-Digital Converter

A Level-Crossing Flash Asynchronous Analog-to-Digital Converter

Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity

Analog-to-Digital Conversion

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