A Level-Crossing Flash Asynchronous Analog-to-Digital Converter

Akopyan, F.; Manohar, Rajit; Apsel, Alyssa

doi:10.1109/async.2006.5

Cited by 84 publications

(47 citation statements)

References 24 publications

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“…Level crossing ADC architectures in previous literature can be generally classified into two types: LC ADC using feedback DAC [2], [3], [5] and LC ADC with flash ADC like architecture [4]. A general architecture of LC ADC using feedback DAC consists of feedback DAC, comparators, counter and timer as shown in the figure 1.…”

Section: Previous Literaturementioning

confidence: 99%

Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

Antony¹

2018

IJRASET

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This paper presents the design of a charge sharing 1 bit DAC with pseudo resistors suitable for an asynchronous level crossing ADC. Dummy NMOS devices are added to the 1 bit DAC for reducing the charge accumulation and clock feed through giving a 81.26 % increase in SFDR for 5 kHz input frequency compared to the 1 bit DAC with only pseudo resistors. The asynchronous control logic for the DAC is designed digitally and optimized for lower power consumption. The DAC and its control logic has been designed using 180nm technology in cadence using a supply voltage of 0.8 V and consumes an average power of 2.323 nW. Keyword: Digital to Analog Converters (DAC), Analog to Digital Converters (ADC), Asynchronous, Level crossing, pseudo resistors I. INTRODUCTIONAsynchronous ADC architectures are emerging as an excellent alternative for replacing synchronous ADCs in various applications such as portable and implantable biomedical signal sensing devices, remote environmental monitors and sensors, military applications, magnetic disk reader, optical disk readers and wireless applications such as audio devices and cellular telephones. The advantages of asynchronous circuits compared to their synchronous counter parts are higher speed, lower power consumption, and smaller area, immunity to metastable behaviour, less clock skew and low susceptibility to electromagnetic interference. Level crossings ADCs are asynchronous ADCs that generate output samples only when the input signal crosses a threshold level [1]. Level crossing ADCs offers lower sampling rate, power consumption and area than synchronous ADCs. Level crossing ADC has been mainly used in embedded sensing systems, such as environmental sensors (temperature, pressure sensors), implantable biomedical applications, hearing aids and ultrasound applications [2]- [7], [10],[ 11]. This paper presents the design of a charge sharing 1 bit DAC with pseudo resistors and additional dummy NMOS devices for a level crossing ADC. A digital DAC logic using gates and latches for the control of the 1 bit DAC asynchronously is also designed in this paper. In this paper, section II discusses previous literatures on DAC used in level crossing ADCs. Section III gives the circuit implementation followed by results and discussion in section IV. Section V gives the conclusion of the paper.

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Section: Previous Literaturementioning

confidence: 99%

Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

Antony¹

2018

IJRASET

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“…Nr i is the number of resampled data points that lie in the ith selected window. Thus, the time resolution Δt i and the frequency resolution Δ f i of the proposed STFT can be specific for the ith selected window and are defined by (12) and (13), respectively. Because of this adaptive resolution, the proposed STFT will be named as the adaptive resolution STFT, (ARSTFT) throughout the following parts of this article.…”

Section: Adaptive Resolution Analysismentioning

confidence: 99%

“…In this context, analog to digital converters based on the LCSS have been developed [10][11][12]. The AADC [10] is employed for digitizing x(t).…”

Section: Asynchronous Analog To Digital Converter (Aadc)mentioning

confidence: 99%

An Adaptive Resolution Computationally Efficient Short‐Time Fourier Transform

Qaisar

Fesquet

Renaudin

2008

Journal of Electrical and Computer Engineering

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The short-time Fourier transform (STFT) is a classical tool, used for characterizing the time varying signals. The limitation of the STFT is its fixed time-frequency resolution. Thus, an enhanced version of the STFT, which is based on the cross-level sampling, is devised. It can adapt the sampling frequency and the window function length by following the input signal local characteristics. Therefore, it provides an adaptive resolution time-frequency representation of the input signal. The computational complexity of the proposed STFT is deduced and compared to the classical one. The results show a significant gain of the computational efficiency and hence of the processing power.

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“…As a result, most of the power is wasted; in signal processing terms, the signal is non-stationary and therefore the optimal sampling rate should be adapted based on the signal characteristics [3]. As many real-world signals vary irregularly, and asynchronous circuit processes only these relevant brief periods.…”

Section: Introductionmentioning

confidence: 99%

Design of resolution/power controllable Asynchronous Sigma-Delta Modulator

Deshmukh

2016

EURASIP J. Adv. Signal Process.

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This paper presents the design of a Programmable Asynchronous Modulator (PAM) with field control of resolution and power. A novel variable hysteresis Schmitt Trigger (ST) is used for external programmability. Asynchronous Sigma-Delta Modulator (ASDM) implementation with external control voltages is proposed to supervise the resolution and power. This architecture with reduced circuit complexity considerably improves the earlier realizations by eliminating multiple current sources as well switched capacitor circuits and results in power saving up to 87 %. Proposed PAM design demonstrates an improved SNDR of 115 dB, DR of 96 dB, and power consumption below 280 μW. It illustrates Effective Number of Bits (ENOB) to 18.81 and Figure of Merit (FoM) to 0.15 fJ/conversion step. Modulator is implemented in Cadence UMC Hspice 0.18 μm CMOS analog technology. Off-chip PAM control for resolution/power performance has potential applications in battery operated ultra low power applications like IoT; where ADC is one of the major power consuming components. It offers the promise for an efficient performance with power saving.

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A Level-Crossing Flash Asynchronous Analog-to-Digital Converter

Cited by 84 publications

References 24 publications

Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

Design of an Asynchronous 1 Bit Charge Sharing Digital to Analog Converter for a Level Crossing ADC

An Adaptive Resolution Computationally Efficient Short‐Time Fourier Transform

Design of resolution/power controllable Asynchronous Sigma-Delta Modulator

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