A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $\mu{\hbox {m}}$ CMOS Technology

Yu, Jianjun; Dai, Fa Foster; Jaeger, R.C.

doi:10.1109/jssc.2010.2040306

Cited by 185 publications

(68 citation statements)

References 13 publications

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“…To realize sub-gate-delay resolution, a Vernier TDC architecture [14] is widely adopted thanks to the simplicity of its design concept [15,16,17,18]. As illustrated in Fig.…”

Section: Time-to-digital Convertersmentioning

confidence: 99%

“…By tuning the delay difference T LSB ¼ t 1 À t 2 , we can realize fine time resolution. With this concept some novel architectures such as Vernier delay rings or two-dimensional Vernier configurations have been reported [15,16]. This architecture, however, requires two independent delay lines, where mismatch between them is inevitable.…”

Section: Time-to-digital Convertersmentioning

confidence: 99%

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Time-domain approach for analog circuits in deep sub-micron LSI

Asada

Nakura²,

Iizuka

et al. 2018

IEICE Electron. Express

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As the scaling of LSI is going to extremely fine regions toward the ultimate feature size, one of difficulties faced in analog circuit design is reduction of the dynamic range (DR) due to the supply voltage reduction. Unlike digital circuits, where the noise margin for logic operation is the key criterion, analog circuits need an enough DR. The reduced supply voltage directly results in DR degradation of the conventional analog circuits in the voltage-domain. Especially in mixed-signal LSIs, supply voltage instability, caused by logic operation, tends to degrade DR further. In this paper, we will first discuss potential capability of a new paradigm of time-domain circuits by comparing with the conventional voltage/current-domain circuits in terms of DR and power consumption. Next, as basic circuit components for the time-domain approach, current status of TDA (Time-Difference Amplifier) and TDC (Time-to-Digital Converter) will be reviewed. Finally, some application examples of the time-domain circuits are introduced to demonstrate the feasibility of the time-domain approach.

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“…To realize sub-gate-delay resolution, a Vernier TDC architecture [14] is widely adopted thanks to the simplicity of its design concept [15,16,17,18]. As illustrated in Fig.…”

Section: Time-to-digital Convertersmentioning

confidence: 99%

Section: Time-to-digital Convertersmentioning

confidence: 99%

Time-domain approach for analog circuits in deep sub-micron LSI

Asada

Nakura²,

Iizuka

et al. 2018

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…In a [10], a ring oscillator is frozen [12] by disabling the delay elements. While conventionally this is done by an external signal for all delay elements synchronously, the novel architecture uses the stop signal to freeze the start line in a linear Vernier delay line.…”

Section: Architecturementioning

confidence: 99%

A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter

et al. 2013

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Abstract-A novel Time-to-Digital Converter architecture for high resolution and low power is proposed. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the slow delay line can be frozen by the fast delay line, omitting the powerhungry time capture elements like D-registers or arbiters that are usually employed in a Vernier TDC. The two main issues of the design, the charge kickback between the delay lines and the imperfect freezing are solved with extra circuitry. The overall TDC consists of inverters and transmission gates only. A proof-ofconcept design has been simulated in 90nm CMOS with a typical resolution of 10.05 ps, a dynamic energy consumption of 0.232 pJ per conversion and an area of 10.503 µm 2 .

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“…The output bit of Arbiters controls the fine and coarse counters which were identified as stop bit in Figure 3. Figure 4 describes the schematics of proposed arbiters used in the VTDC [6]. The arbiters need to be reset at each judge before the next comparison starts, so reset circuit is utilized in an arbiter core.…”

Section: The Vernier Tdcmentioning

confidence: 99%

A High Resolution First Order Noise-Shaping Vernier Time-to-Digital Converter

Sorkhabi¹,

Toofan²

2013

AJEEE

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In this paper, we propose a noise reduction method for a Vernier Time-to-Digital Converter (VTDC) using a first-order noise shaping structure and a gated ring oscillator (GRO). An 11bit VTDC with 4 p s effective resolution was designed and developed for a high performance All Digital Frequency Synthesizer (ADFS). The VTDC realized in 180nm CMOS, its power consumption depending on the time difference between input edges; 1 to 11mA from a 1.5 V supply.

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A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $\mu{\hbox {m}}$ CMOS Technology

Cited by 185 publications

References 13 publications

Time-domain approach for analog circuits in deep sub-micron LSI

Time-domain approach for analog circuits in deep sub-micron LSI

A CMOS 0.23pj Freeze Vernier Time-To-Digital Converter

A High Resolution First Order Noise-Shaping Vernier Time-to-Digital Converter

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