A 12-bit 3.125-MHz bandwidth 0-3 MASH delta-sigma modulator

Abstract

Abstract-We demonstrate a 12-bit 0-3 MASH delta-sigma modulator with a 3.125 MHz bandwidth in a 0.18 m CMOS technology. The modulator has an oversampling ratio of 8 (clock frequency of 50 MHz) and achieves a peak SNDR of 73.9 dB (77.2 dB peak SNR) and consumes 24 mW from a 1.8 V supply. For comparison purposes, the modulator can be re-configured as a single-loop topology where a peak SNDR of 64.5 dB (66.3 dB peak SNR) is obtained with 22 mW power consumption. The energy required per conversion step for the 0-3 MASH architecture (0.95 pJ/step) is less than half of that required by the feedback topology (2.57 pJ/step).

A +5dBFS third-order extended dynamic range single-loop ΔΣ modulator

“…The saturation of Q 2 will happen roughly at the 2V ref − LSB 1 above the linear range of the first quantizer, greatly increasing the dynamic range of the modulator. A similar concept has been recently applied to 0-N MASH structures [3]. However, in this structure, the quantization extraction is done at the front-end and its cancelation is done outside the loop via digital filters.…”

A 1.2V, 78dB HDSP ADC with 3.1V input signal range

“…Thanks to the extended redundancy, the enhanced HDSP modulator can tolerate around 0.5dB (0.5dB in measurement and 0.8dB in simulation) over full-range input signals without overloading the residue amplifier. The over-range operation of the HDSP modulator can be further extended by employing techniques introduced in [3] and [4]. In summary, relaxed swing requirements, simplified signal addition and extended built-in redundancy of the enhanced HDSP modulator allow using input signals greater than analog supply voltage without overloading the internal nodes of the modulator.…”

“…However, this will accordingly make the design of high-swing, high-gain amplifiers difficult and also will reduce the Dynamic Range (DR) of the ADC. Relaxed gain and swing requirements of the HDSP modulator [3] make this architecture a good candidate for low voltage operation. The only concern is the full range swing of the residue amplifier in the pipelined quantizer.…”

A 1-V, 82-dB, 2.5-MS/s, single loop, single bit delta-sigma modulator in 0.13-μm CMOS technology

“…It is possible to achieve low OSR with multi-stage loop filter or multi-bit quantizer [5]. Although the multi-stage topology can ease the stability issue for high order Delta-Sigma modulator, high OTA DC gain is required to get a good cancellation for the quantization noise from 1st stage [6]. It becomes more and more difficult to design a high gain OTA with deep sub-micron processes and low supply voltage.…”