A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator

Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR

“…The calculated sub-harmonics agree with simulation results within 0.02 dB. The sensitivity to errors of type 1) and 2) is the same, as the error weights in (22) and (23) are equal, while the error of type 3) is scaled by the nominal full-scale, as shown in (26).…”

“…Recent research in DTCs for low-power fractional PLLs [41]- [43] has led to substantial improvements in DTC performance and has boosted the development of high-speed implementations at GHz frequencies that are suitable for use in DDS systems [25], [26], [29]. Most of these DTCs exploit a constant-slope delay generation [44] and achieve more than 10−bit resolution, a few LSB INL and a FoM down to a few fJ/conversion.…”

“…Since the fastest DTC implementations work at a couple of GHz [25], [26], the system would produce square waves controlled on both edges at maximum 1 GHz. The output frequency can be pushed further with time-interleaving, where different DTCs work in succession.…”

“…12 shows the spectrum in dBc, resulting from behavioral simulations of the proposed system, when errors in the categories 1), 2), 3) have been inserted in the DTC model. In this example, we chose realistic error values of a few LSB, according to the state-of-the-art DTCs [25], [26], [55] The horizontal axis is normalized to the target output frequency. The simulated spectrum of signal M SB before the DTC correction is in yellow, the output spectrum is shown in dark green, and the calculated sub-harmonics with (13), (14) and (27) are shown as light-blue squares.…”

“…In the context of Digital Frequency Synthesis, Delay-Locked Loops (DLLs) have been proposed in the past for deterministic jitter correction [22]- [24], but recently DTCs with sub-pico-second resolution and linearity have become available [25], [26], so they can be used for this purpose.…”