A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration

Ali, Ahmed; Dinc, Huseyin; Bhoraskar, Paritosh; Bardsley, Scott; Dillon, Chris; McShea, Matthew; Periathambi, Joel Prabhakar; Puckett, Scott

doi:10.1109/jssc.2020.3023882

Cited by 88 publications

(23 citation statements)

References 13 publications

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“…Fig. 15 shows the detailed implementation of the input buffer, a pseudo-differential complementary push-pull source follower topology is adopted, which doubles g m /I d [20], [21]. The bias voltage of the NMOS and PMOS input devices are generated using the current source developing voltages across high-valued resistor that is bypassed with large feed-forward capacitor.…”

Section: Push-pull Input Buffermentioning

confidence: 99%

“…To reduce the high-frequency no-linearity resulting from the drain-to-source voltage variation, the input transistors bootstrap their drain by using one-level cascode devices whose gates are connected to the input through a feedforward capacitor. The backgates of the various transistors are bootstrapped to further improve the buffer linearity [20], the backgates of the input devices are locally tied to their sources, and the backgates of the cascode devices are tied to the equivalent small-signal points on the complementary side. The input buffer is powered by 1.7 and -0.8 V supply rails, which is sufficient to satisfy the linearity requirement of a 1.2-V differential input swing.…”

Section: Push-pull Input Buffermentioning

confidence: 99%

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A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

Wang

et al. 2022

IEEE Trans. Circuits Syst. I

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This paper presents an improved correlationbased timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step.

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Section: Push-pull Input Buffermentioning

confidence: 99%

Section: Push-pull Input Buffermentioning

confidence: 99%

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

Wang

et al. 2022

IEEE Trans. Circuits Syst. I

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“…Applications like wireless communications and Ethernet networks are in great demand for ultra-highspeed ADCs (or RF ADCs) [40][41][42][43]. Both academia and industry paid extensive efforts to promote the development of RF ADCs in the past decades from the following three aspects.…”

Section: Ic Design Law For Ultra-high Speed Adcmentioning

confidence: 99%

Recent progress of integrated circuits and optoelectronic chips

Xiang

Han

Zhang

et al. 2021

Sci. China Inf. Sci.

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Integrated circuits (ICs) and optoelectronic chips are the foundation stones of the modern information society. The IC industry has been driven by the so-called "Moore's law" in the past 60 years, and now has entered the post Moore's law era. In this paper, we review the recent progress of ICs and optoelectronic chips. The research status, technical challenges and development trend of devices, chips and integrated technologies of typical IC and optoelectronic chips are focused on. The main contents include the development law of IC and optoelectronic chip technology, the IC design and processing technology, emerging memory and chip architecture, brain-like chip structure and its mechanism, heterogeneous integration, quantum chip technology, silicon photonics chip technology, integrated microwave photonic chip, and optoelectronic hybrid integrated chip.

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“…Likewise, [7] proposed a background calibration technique based on adaptive filters to compensate for the nonlinearity of analog circuits in the ADC. More comprehensive calibration techniques have enabled new regime of high-performance ADCs [8]. Similarly, advanced digital predistortion and noise shaping techniques have been developed for wideband and high dynamic range digital-to-analog converters (DACs) [9]- [11].…”

Section: A Digitally-assisted Ams Designmentioning

confidence: 99%

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms

Su¹,

Zhang²,

Hassanpourghadi³

et al. 2021

Preprint

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Analog mixed-signal (AMS) circuit architecture has evolved towards more digital friendly due to technology scaling and demand for higher flexibility/reconfigurability. Meanwhile, the design complexity and cost of AMS circuits has substantially increased due to the necessity of optimizing the circuit sizing, layout, and verification of a complex AMS circuit. On the other hand, machine learning (ML) algorithms have been under exponential growth over the past decade and actively exploited by the electronic design automation (EDA) community. This paper will identify the opportunities and challenges brought about by this trend and overview several emerging AMS design methodologies that are enabled by the recent evolution of AMS circuit architectures and machine learning algorithms. Specifically, we will focus on using neural-network-based surrogate models to expedite the circuit design parameter search and layout iterations. Lastly, we will demonstrate the rapid synthesis of several AMS circuit examples from specification to silicon prototype, with significantly reduced human intervention.

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A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration

Cited by 88 publications

References 13 publications

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

Recent progress of integrated circuits and optoelectronic chips

Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms

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