A 12 b 128 MSample/s ADC with 0.05 LSB DNL

Jewett, R.; Poulton, K.; Hsieh, Kuo-Chiang; Doernberg, J.

doi:10.1109/isscc.1997.585305

Cited by 39 publications

(11 citation statements)

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“…The convergence time depends crucially on the specific extraction algorithm used. Currently, the sequential iterative method [6], [7] or certain signal averaging method [8]- [13] is used, but in our work of [3], we use a different method, which is the key to our fast convergence solution, as we will see shortly. To see how the iterative algorithm or the currently used averaging differs from our fast-convergence solution, let us first obtain a frequency domain picture of ∆ in [n] of (1).…”

Section: A Frequency Domain Analysis Of Correlation-based Backgroundmentioning

confidence: 99%

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Surpassing Tradeoffs by Separation: Examples in Transmission Line Resonators, Phase-Locked Loops, and Analog-to-Digital Converters

Sun¹,

Andress²,

Woo³

et al. 2008

JSTS:Journal of Semiconductor Technology and Science

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We review three examples (an on-chip transmission line resonator [1], a phase-locked loop [2], and an analog-todigital converter [3]) of design tradeoffs which can in fact be circumvented; the key in each case is that the parameters that seem to trade off with each other are actually separated in time or space. This paper is an attempt to present these designs in such a way that this common approach can hopefully be applied to other circuits. We note reader that this paper is not a new contribution, but a review in which we highlight the common theme from our published works [1]-[3]. We published a similar paper [4], which, however, used only two examples from [1] and [2]. With the newly added content from [3] in the list of our examples, the present paper offers an expanded scope.

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Section: A Frequency Domain Analysis Of Correlation-based Backgroundmentioning

confidence: 99%

“…algorithm [6], [7] and the averager [8]- [13]): the bandwidth is fixed and the tradeoff is directly faced. To satisfy a required accuracy, the LPF bandwidth is set small enough, resulting in a long convergence time.…”

Section: B Fast Convergence Techniquementioning

confidence: 99%

Surpassing Tradeoffs by Separation: Examples in Transmission Line Resonators, Phase-Locked Loops, and Analog-to-Digital Converters

Sun¹,

Andress²,

Woo³

et al. 2008

JSTS:Journal of Semiconductor Technology and Science

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show abstract

“…This is utilized to investigate the signal feedthrough from the output to the input by adding the possibility of scrambling the outgoing digital words with a pseudorandom bit-stream [229]. The scrambling is realized by putting XOR gates before each output buffer and applying the random bit to their other input.…”

Section: Digital Offset Calibrationmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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“…Dynamic element matching (DEM) digital to analog converters (DACs) [8]- [9] have enabled major performance improvements over the oversampling delta-sigma data converters, pipelined ADCs, and high resolution Nyquist-rate DACs.…”

Section: Introductionmentioning

confidence: 99%

Implementation of dynamic element matching DAC and its use for noise cancellation in ΔΣ fractional-N PLL

Hati

Bhattacharyya

2014

2014 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2014]

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This paper shows the design of a 12 bit dynamic element matching (DEM) DACs which eliminates pulse shape, timing, and amplitude errors arising from component mismatches as sources of non-linear distortion in high resolution DACs. This has been proved through analytical and simulation results in 0.18 m standard CMOS process. A set of sufficient conditions of the DEM encoder that ensure this effect, and a specific segmented DEM encoder that satisfies the sufficient conditions are presented here. Unlike the most previously published fully randomized DEM encoders, the complexity of this design does not grow exponentially with the number of bits of DAC resolution. Part of this DEM DAC may be included in noise cancellation circuit in ΔΣ fractional-N PLL. Analytical results are demonstrated with simulation results. Additionally, this paper provides the explanation of noise cancellation in ΔΣ fractional-N PLL and power dissipation versus circuit complexity trade off.Keywords-Dynamic element matching, digital-to-analog converters, ΔΣ fractional-N PLL, high resolution data converters, high linearity, delta sigma MASH divider, quantization noise.

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A 12 b 128 MSample/s ADC with 0.05 LSB DNL

Cited by 39 publications

References 1 publication

Surpassing Tradeoffs by Separation: Examples in Transmission Line Resonators, Phase-Locked Loops, and Analog-to-Digital Converters

Surpassing Tradeoffs by Separation: Examples in Transmission Line Resonators, Phase-Locked Loops, and Analog-to-Digital Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Implementation of dynamic element matching DAC and its use for noise cancellation in ΔΣ fractional-N PLL

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A 12 b 128 MSample/s ADC with 0.05 LSB DNL

Cited by 39 publications

References 1 publication

Surpassing Tradeoffs by Separation: Examples in Transmission Line Resonators, Phase-Locked Loops, and Analog-to-Digital Converters

Surpassing Tradeoffs by Separation: Examples in Transmission Line Resonators, Phase-Locked Loops, and Analog-to-Digital Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Implementation of dynamic element matching DAC and its use for noise cancellation in &#x0394;&#x03A3; fractional-N PLL

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Implementation of dynamic element matching DAC and its use for noise cancellation in ΔΣ fractional-N PLL