A 12-B 10-Msamples/S Cmos Switched-Current Delta-Sigma Modulator

We present in this work a systematic analysis to identify Sigma Delta Modulators (∑ΔMs) non-idealities, such as charge injection error, Input/Output conductance ratio error and settling time error. A physical mechanism behind Switched Current (SI) errors is proposed. In the first time, errors mentioned above are treated separately and a behavioural model of SI cell is derived for each non-ideality. In the second time, we propose a behavioural model of Non-inverting Lossless Integrator. For typical variations of SI-related errors, simulations have been made using Matlab/Simulink. Finally we present their influences on both dynamic and static performances of the 2nd order SI Low Pass ∑ΔMs (SI-LP∑ΔMs).

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A 12-B 10-Msamples/S Cmos Switched-Current Delta-Sigma Modulator

Cited by 2 publications

References 6 publications

Prospect of the future of switched-current circuits with regard to future CMOS technologies

Prospect of the future of switched-current circuits with regard to future CMOS technologies

Switched-Current Techniques: An Overview of Cumulative SI-Related Errors on Dynamic and Static Performances of 2nd Order LP-ΣΔMs

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