A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

Menoifi, Christian; Braendli, Matthias; Francese, Pier Andrea; Morf, Thomas; Cevrero, Alessandro; Kossel, Marcel; Kull, Lukas; Luu, Danny; Özkaya, İlter; Toifl, Thomas

doi:10.1109/isscc.2018.8310205

Cited by 48 publications

(22 citation statements)

References 4 publications

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“…4(b). Conversely, for BFSK amplitudes above f max , the side-channel becomes limited by its frequency modulation slope from (4). As shown in Figs.…”

Section: Side-channel Design Parametersmentioning

confidence: 92%

“…Typically, the RX would employ adaptation algorithms to optimize their highly programmable equalizers to minimize bit error rate (BER) and power during operation [2], [3]. Highly programmable TXs are also available; however, without channel information, they can only be initialized to nominal settings at start-up, and cannot be dynamically adapted during operation [4]. TX adaptation can enable higher data rates while keeping power low.…”

Section: Introductionmentioning

confidence: 99%

“…TX adaptation can enable higher data rates while keeping power low. For example, accurately setting the TX equalizer in [4] allowed the use of a simplified and very low-power RX architecture in [5]. To facilitate this, a secondary communication link, i.e., a backchannel, would be required to permit the RX to transmit control bits embedding information, such as ISI, channel response, BER, process variation, and temperature back to the TX.…”

Section: Introductionmentioning

confidence: 99%

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Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

Zhang

Liang

Shahramian

et al. 2020

IEEE Solid-State Circuits Lett.

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A secondary communication link, or side-channel, is proposed, which uses binary frequency shift keying to modulate the frequency of a high-speed wireline transmitter clock. This side-channel data is then received using the corresponding receiver's conventional clock and data recovery (CDR) circuit. An analysis of the CDR loop parameters demonstrates that, within certain limits, the side-channel does not impact the signal integrity of the primary high-speed data. Measurements were made on a side-channel prototype using a 56-Gb/s PAM-4 (half-rate 14-GHz clock) transceiver in 7-nm FinFET technology through a 15-dB loss channel. Over 10 4 side-channel bits were transmitted at 50 kb/s, and the side-channel remained error-free with no visible impact on the high-speed link.

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“…4(b). Conversely, for BFSK amplitudes above f max , the side-channel becomes limited by its frequency modulation slope from (4). As shown in Figs.…”

Section: Side-channel Design Parametersmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

Zhang

Liang

Shahramian

et al. 2020

IEEE Solid-State Circuits Lett.

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“…Today, 100 Gb/s communication per channel is achieved using digital pre-equalizers and DAC at the transmitter [3] and a combination of CTLE, ADC, and digital equalizer at the receiver. This data rate is achieved in conjunction with PAM-4 modulation [1] and in combination with partial response signaling [4].…”

Section: Introductionmentioning

confidence: 99%

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication

Salinas

Cosson-Martin

Laghaei

et al. 2021

IEEE Open J. Circuits Syst.

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Limits of data rate over a wireline channel depend on the channel characteristics, the signaling or modulation scheme, and the complexity one can afford for its implementation. This article compares two signaling schemes, namely baseband and discrete multi-tone (DMT), for two example channels, one with a smooth frequency response and one with a notch frequency response, to examine how far each can push the data rate towards the maximum achievable data rate, derived from Shannon Capacity formula. INDEX TERMS Discrete multi-tone (DMT), pulse amplitude modulation (PAM), quadrature amplitude modulation (QAM), Shannon's capacity, bit loading, salz SNR, integrated crosstalk noise (ICN), insertion loss (IL).

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“…Several techniques can be used to compensate the channel effect on serial links. Continuous Time Linear Equalization (CTLE) [1]- [3], Feed-Forward-Equalizer (FFE) [4], [5], and Decision Feedback Equalizer (DFE) [6], [7]. FFE is used to increase the amplitude of the high-frequency components at the transmitter.…”

Section: Introductionmentioning

confidence: 99%

Adaptation of Feed-Forward Equalizer Settings: A Frequency Domain Analysis Approach

Zaki¹

2019

IJCDS

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Characteristics of the channel has a major effect on the signal integrity. The channel distortion is increased with high-rate data transmission. Feed-Forward Equalizer (FFE) at transmitter side is one of the methods that can be used to compensate the effect of the channel. PCIe-Gen3, 4, and 5 standards specify some constraints on the FFE settings and assign some preset values that can be used based on the effect of FFE on time-domain. In this paper, detailed analysis for the FFE in frequency domain is presented. New preset values are recommended to achieve enhancement on the behavior over different channels. Short and long channel models are created based on the PCIe standard specifications to check the suggested preset values with worst channels. Continuous-Time Linear Equalizer (CTLE) also is modeled to check the effect of FFE with different CTLE boost values. The eye-measurements based on the new preset values is enhanced by 10% with respect to the default preset values in PCIe specifications for short and long channel. Mapping the preset value in the frequency domain helps fine tuning process for FFE settings by facilitating more guidance to get the best FFE settings.

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A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

Cited by 48 publications

References 4 publications

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication

Adaptation of Feed-Forward Equalizer Settings: A Frequency Domain Analysis Approach

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