Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication

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This paper proposes a discrete multi-tone timing-recovery system with adaptive equalization for ultra-high-speed wireline applications. It combines frequency-domain clock recovery with decisiondirected equalization to improve receiver performance while eliminating the need for pilot carriers, thereby increasing spectral efficiency. Compared to a conventional pilot-carrier-based technique employing four pilot carriers and a 32-point FFT, this approach improves phase-error sensitivity by 3.6 times, tracking bandwidth by 1.7 times, increases the jitter tolerance slope by 20dB per decade at low frequency, and removes residual equalization error, resulting in an overall data-rate increase of 27%. The concept is validated at the system-level and gate-level through synthesis in an FPGA. A convergence analysis of both the adaptive equalizer and clock synchronization shows the system's ability to mitigate error propagation and remain synchronized in the presence of impairments. Finally, we highlight the system's ability to trade-off clock convergence versus phase error sensitivity. Either parameter can be adjusted by 15 times, optimizing the receiver over a broad range of signal conditions.INDEX TERMS Adaptive equalization, clock and data recovery (CDR), decision-directed equalization, discrete multi-tone (DMT), orthogonal frequency division multiplexing (OFDM), SERDES, single-tap equalization, timing recovery, wireline. JEREMY COSSON-MARTIN (Graduate Student Member, IEEE) received the B.A.Sc. degree in electrical engineering from Queen's University, Kingston, ON, Canada, in the spring of 2018. In the fall of 2018, he began an M.A.Sc. program at the University of Toronto, ON, Canada, under the supervision of Prof. A. Sheikholeslami. In 2019, he transferred into a Ph.D. program.In the summer of 2018, he joined Huawei Canada, Toronto, ON, Canada, as an intern, where he was involved in creating in-lab measurement scripts for a prototype 56-Gb/s SerDes integrated chip. He also received experience in 7-nm FinFET layout. Currently, he is researching multi-tone schemes for ultra-high-speed wireline applications.

Section: B Equalizationmentioning

confidence: 99%

Section: A Adaptive Equalizer Stabilitymentioning

confidence: 99%

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Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Cosson-Martin

Shakiba

Sheikholeslami

2021

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“…W IRELINE data rates are marching beyond 200Gb/s [1], but a question remains as to how much room is left in this march and how to close the remaining gap to Shannon's capacity limit [2]. In the pursuit to close this gap, alternative signal modulation techniques are being considered, including multi-carrier schemes [3][4] [5][6] [7] [8].…”

Section: Introductionmentioning

confidence: 99%

An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications

Cosson-Martin

Shakiba

Sheikholeslami

2022

Self Cite

This paper proposes an efficient multi-carrier system that combines filter-bank multi-carrier signalling, decision-directed channel estimation, and frequency-domain timing recovery to eliminate the overhead associated with cyclic prefix, large side-lobes, and pilot carriers. Furthermore, a technique is proposed to halve the required number of FFTs (IFFTs), reducing their complexity by 29% for a 32-point resolution; a method is proposed to correct tilt and stretch distortion; and a gain controller with adaptive loop coefficients is adopted to achieve the same stability but 65% higher tracking bandwidth regardless of the FFT size. The concept is validated at the system level, where impairments are applied, enabling an in-depth comparison to conventional discrete multi-tone signalling. Assuming a 32-point FFT, a 35dB channel, and an overlap factor of 3, results show 101% improvement in capacity, 100% improvement in power efficiency, and 101% improvement in area efficiency, and all while maintaining comparable latency. This work enables very low-resolution multi-carrier schemes, which were previously impractical due to the significant overhead.

“…Prior-arts such as [19], [20] showed that 56-112 Gb/s optical data communication is feasible with discrete multi-tone (DMT) modulation (i.e., baseband OFDM with variable bit-loading for each OFDM sub-channel), and [21] demonstrated a 56 Gb/s RX data-path silicon for electrical links. System-level modeling of a DMT serial link for > 100 Gb/s applications is provided in [22], and [23] compared DMT link and PAM-2/4/8 for ultra-high-speed links both with smooth channels and multi-drop-bus (MDB) interfaces. Timing recovery system with adaptive equalization for wireline DMT links is proposed in [24].…”

Section: Introductionmentioning

confidence: 99%

Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications

Kim

2022

The 4-level pulse-amplitude modulation (PAM-4) with an analog-digital converter (ADC)-based receiver (RX) has become the most commonly employed modulation for ultra-high-speed serial links with the data rate above 100 Gb/s. To support the data rate of 200 Gb/s, orthogonal frequency division multiplexing (OFDM) has been studied recently as one of the possible modulation schemes in the next-generation serial links. The OFDM can feature high bandwidth efficiency without increasing the equalization complexity, leading to a reduced maximum signal amplitude attenuation and lower required DAC/ADC conversion rates given sufficient DAC/ADC resolutions such that the BER is not primarily limited by the data converters' resolution. This paper presents system-level modeling results of OFDM-based wireline serial links, with a particular emphasis on the impacts of the fast Fourier transform (FFT) processor's tap count on the serial link performance. The relationship among the cyclic prefix (CP), FFT tap count, and the link bit-error-rate (BER) are thoroughly explained. The analysis explains that the power consumption of a partially-serial FFT processor improves with a larger kernel FFT size, and simulation results show that the BER performance improves with the FFT size where an optimal CP length exists given the FFT size.