A 10b 120MS/s 45nm CMOS ADC using A re-configurable three-stage switched op-amp

Kim, Young‐Ju; Lee, Kyung-Hoon; Ji, Seung-Hak; Kwon, Yi-Gi; Lee, Seung‐Hoon; Moon, Kyong Whan; Choi, Michael; Park, Ho‐Jin; Park, Byeong-Ha

doi:10.1109/cicc.2010.5617409

Cited by 2 publications

(2 citation statements)

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“…A three-stage amplifier has been proposed to achieve the required high gain; however, the multi-stage amplifier needs a complex frequency-compensation technique to remove zeros in the right-half plane, affecting the stability of the overall system. As a result, the circuits become complicated; moreover, the area and power consumption of the amplifier are correspondingly increased [5].…”

Section: Proposed Process-insensitive Amplifiermentioning

confidence: 99%

“…Recently, the amplifier sharing technique with two separate differential pairs has been employed to remove the input memory effect caused by having no extra reset the input summing nodes of an amplifier [5]. However, it suffers from the performance degradation due to the internal input switching operating of the amplifier.…”

Section: Proposed Process-insensitive Amplifiermentioning

confidence: 99%

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10b 150MS/s 0.4mm<sup>2</sup> 45nm CMOS ADC based on process-insensitive amplifiers

Park

Kim

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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A 10b 150MS/s 0.4mm 2 pipeline ADC is implemented in a 45nm CMOS process. The input SHA, employing four charge-redistributed capacitors, converts single-ended or differential input signals of 1.2Vpp to differential outputs of 0.8Vpp for a low supply voltage of 1.1V. The process-insensitive high-gain amplifiers in the SHA and MDACs are based on gainboosting, pseudo-differential output pair, and continuous-time common-mode feedback circuits to overcome various performance limitations that are observed in deep nanometer CMOS technologies. The MDAC2 and MDAC3 share a single high-gain amplifier to reduce the input memory effect, chip area, and power dissipation. The measured DNL and INL are within 1.06 and 1.29LSB, respectively. At 150MS/s, the prototype ADC shows a maximum SNDR of 51.8dB and a maximum SFDR of 63.7dB with a 1.2Vpp sinusoidal input and consumes 47.3mW.

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Section: Proposed Process-insensitive Amplifiermentioning

confidence: 99%

Section: Proposed Process-insensitive Amplifiermentioning

confidence: 99%