A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Amplifier

Abstract

Present-day smartphones and tablets demand high audio fidelity (e.g., total harmonic distortion + noise, THD + N 0.01%), and high noise immunity (e.g., power supply rejection ratio, PSRR 80 dB) to allow high integration in an SoC. The design of conventional closed-loop pulse width modulation (PWM) Class-D amplifiers (CDAs) typically involves undesirable trade-offs between fidelity (qualified by THD + N), PSRR and switching frequency. In this paper, we propose a fully integrated CMOS CDA that embodies a novel input-modulated carrier generator and a novel phase-error-free PWM modulator, collectively allowing the employment of high loop-gain to achieve high PSRR, yet without compromising linearity/dynamic-range or resorting to high switching frequency. The prototype CDA, realized in 65 nm CMOS, achieves a THD + N of 0.0027% and a power efficiency of 94% when delivering 500 mW to an 8 Ω load from V = 3.6 V. The PSRR of the prototype CDA is very high, -101 dB @217 Hz and 90 dB @1 kHz, arguably the highest to-date. Furthermore, the switching frequency of the prototype CDA varies from 320 to 420 kHz, potentially reducing the EMI due to spread-spectrum. In addition, the prototype CDA is versatile with a large operating-voltage range, with V ranging from rechargeable 1.2 V single battery to standard 3.6 V smart-device supply voltages.

An Ultralow-Power Overcurrent Protection Circuit for Micropower Class D Amplifiers

“…For example, their power-efficiency, ƞ, can exceed 90% at full signal swing (modulation index, M=1) [1,2].…”

Design of Multioctave High-Efficiency Power Amplifiers Using Stochastic Reduced Order Models

“…To achieve a high-efficiency PA, designs reported in the literature have adopted techniques such as class E [1]- [8], class D [9], [10], class F/F −1 [11]- [16], and Doherty structures [17]- [21]. Although these methods enhance the efficiency of a PA, the requirement on accurate waveform engineering would restrict the bandwidth.…”

Analysis and design of audio class D amplifiers

“…A number of contributions are made in this Ph.D. program and they are largely reported in our technology disclosures and ensuing patents [38][39][40], and journal [41][42][43] and conference publications [44][45][46][47]. To the best of the author's knowledge, all contributions delineated herein are novel and unreported in literature.…”

“…A large portion of this chapter has been published as a US provisional patent [38] and published in IEEE Journal of Solid State Circuits [42]. To circumvent said undesirable trade-offs, we propose a novel PWM CDA architecture that, as depicted in Figure 4-2, embodies an input-modulated carrier generator and a phase-error-free PWM modulator (see Figure 4-5 (a) later).…”