A 100 W 5.1-Channel Digital Class-D Audio Amplifier With Single-Chip Design

Liu, Jiaming; Chien, Shih-Hsiung; Kuo, Tai‐Haur

doi:10.1109/jssc.2012.2188465

Cited by 26 publications

(25 citation statements)

References 17 publications

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“…Table 1 summarizes the simulation results of the proposed class-D audio amplifier in comparison with other class-D audio amplifiers in [17][18][19][20][21]. Based on our simulation results, which are shown in Table 1, the proposed class-D audio amplifier has an improvement compared to class-D audio amplifier in [17][18][19][20][21] in terms of THD, efficiency, and bandwidth. Although, the SNR comparison shows that this parameter is decreased by about 15% compared to [21], but the output power and bandwidth are increased by about 70% compared to [21].…”

Section: Comparisonmentioning

confidence: 95%

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Design of Novel Low-Power and High-Efficiency Class-d Audio Amplifier

Hajhashemkhani¹,

Karimi²,

Rezai³

2017

IJCA

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Section: Comparisonmentioning

confidence: 95%

“…However, unwanted harmonic in this method is lower than the PWM method [6]. Several methods and structures have been proposed to increase the efficiency of class-D amplifiers based on its stages [7][8][9][10][11][12][13][14][15][16][17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

Design of Novel Low-Power and High-Efficiency Class-d Audio Amplifier

Hajhashemkhani¹,

Karimi²,

Rezai³

2017

IJCA

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“…High-power class-D audio amplifier is gradually popular among TV and home theatre sets because of its high efficiency [1]- [5]. However, its ability of high power delivery may also possibly over-heat itself because the power-loss of amplifier is increasing fast with the power demand, and therefore highlights the importance of system reliability.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Power-Loss Reduction for Over-Temperature Protection of Multilevel Class-D Amplifier

Hsieh¹,

Lin²

2013

IJCEE

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Abstract-Class-D amplifier has been a popular device because of its high power efficiency. However, its ability of high power delivery also brings about over-temperature problem caused by consuming large power-loss over a long time. This paper therefore presents a control method to dynamically reduce the total power-loss of multilevel class-D amplifier according to the value of integrated temperature sensor. The driving (static) power-loss is reduced by limiting the driving current which can be achieved by reducing the output levels of the amplifier. In addition, the switching (dynamic) power-loss is diminished by segmenting the power transistors and gate drivers and selectively enabling parts of them according to the power demand. Therefore, the total power-loss of the amplifier is well controlled and reduced in order to prevent over-heating itself. Under the protection scheme, experimental results show that the total power-loss (excessive heat) and corresponding temperature difference on package can be reduced to only 15% of maximum value which demonstrates the effectiveness of proposed scheme.

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“…These actuators are largely capacitive and the reactive power applied on them can go to several tens of Watts. High-voltage, high-power class-D amplifiers [2][3][4][5] are ideal drivers for such loads, because of their high power efficiency. Preferably, efficiency should be high both at maximum power and at average output power.…”

mentioning

confidence: 99%

“…Obtaining high power efficiency over the full output power range of a class D amplifier is the main focus of this work. [2][3][4][5]. The three main dissipation sources in the power stage are then: 1) Conduction loss P con caused by the output current I out due to r on switch resistance, 2) Ripple loss P Irip caused by the inductor ripple current I rip due to r on and magnetic core loss of L out .…”

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confidence: 99%

17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation

Zee

Nauta

2014

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

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Piezoelectric actuators are widely used in smart materials for vibration and noise control, precision actuators, etc. [1]. These actuators are largely capacitive and the reactive power applied on them can go to several tens of Watts. High-voltage, high-power class-D amplifiers [2][3][4][5] are ideal drivers for such loads, because of their high power efficiency. Preferably, efficiency should be high both at maximum power and at average output power. Obtaining high power efficiency over the full output power range of a class D amplifier is the main focus of this work. caused by the output current I out due to r on switch resistance, 2) Ripple loss P Irip caused by the inductor ripple current I rip due to r on and magnetic core loss of L out . 3) Switching loss P sw at the V pwm node caused by M HS /M LS having to charge/discharge C p in Fig. 1. This can be significant for high V DDP , since the energy stored in C p is proportional to 2 DDP V .There are two scenarios for P sw , depending on I rip and I out . In the first case, for low I out , the inductor ripple current I rip is large enough for the total inductor current L rip out I =I +I to be bidirectional. Then, when , I L can fully charge and discharge C p during the dead time t d without resorting to M HS /M LS . This is the soft switching case where P sw is eliminated. P Irip is now the main dissipation source, and f sw should be high to reduce I rip and thus P Irip . In the second case, when out rip I >I , I L is unidirectional and one of the V pwm switching transitions has to be finished by M HS /M LS . This is the hard switching case where P con and P sw are dominant. Then, the power MOSFET sizing for balanced P con and P sw plays a role, which benefits fromchoosing a low f sw to reduce P sw . We see that the two cases above have contradicting demands on f sw .Common practice is to set f sw in between as a compromise [3], but this is not optimal.Varying f sw can achieve higher efficiency over a larger output power range as in [6] and [7], but both techniques choose f sw based on output current only. This is suboptimal since the dissipation is highly dependent on both I rip and I out , and there are numerous factors causing I rip variation. Apart from external factors like V DDP and L out value, this is especially the case for class-D designs where I rip changes a factor >5 in the 0.05-0.95 duty cycle (D) range.We propose to regulate the I rip amplitude such that both P sw and P Irip are minimized by changing f sw based on the V pwm level at the turn-on transition of the power switches. This information is directly related to the dissipation sources and is inherent for getting to the optimal f sw , independent of circuit operating conditions affecting I rip . The result is a class-D amplifier with its f sw adapted to achieve minimal dissipation from idle to maximum output power. V pwm is not yet at V DDP when M HS turns on, indicating the existence of P sw and f sw should decrease. By adapting f sw such that either one of the V pwm switching is at the bou...

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A 100 W 5.1-Channel Digital Class-D Audio Amplifier With Single-Chip Design

Cited by 26 publications

References 17 publications

Design of Novel Low-Power and High-Efficiency Class-d Audio Amplifier

Design of Novel Low-Power and High-Efficiency Class-d Audio Amplifier

Dynamic Power-Loss Reduction for Over-Temperature Protection of Multilevel Class-D Amplifier

17.1 An integrated 80V 45W class-D power amplifier with optimal-efficiency-tracking switching frequency regulation

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