A 100 nm node CMOS technology for practical SOC application requirement

Ono, Akemi; Fukasaku, K.; Hirai, Tadayoshi; Koyama, S.; Makabe, M.; Matsuda, Takafumi; Takimoto, Michiya; Kunimune, Yorinobu; Ikezawa, N.; Yamada, Y.; Koba, F.; Imai, K.; Nakamura, Norihiro

doi:10.1109/iedm.2001.979557

Cited by 18 publications

(13 citation statements)

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“…Moreover, the gate tunneling leakage will continue to increase at a much higher rate thus mandating the use of high-k materials other than silicon dioxide to enable the use of thicker oxide thicknesses [18]. For example, NEC's 100 nm process technology has a T ox = 1.6 nm, subthreshold leakage of 0.3 nA/lm, and an NMOS gate tunneling leakage of 0.65 nA/lm [19]. Figure 5 shows the gate tunneling leakage current produced by an SOI NMOS transistor.…”

Section: Gate Tunneling Leakage Currentmentioning

confidence: 98%

Statistical timing and leakage power analysis of PD-SOI digital circuits

Kim

2008

Analog Integr Circ Sig Process

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This paper presents a fast statistical static timing and leakage power analysis in Partially-Depleted Silicon-On-Insulator (PD-SOI) CMOS circuits in BSIM-SOI3.2 100 nm technology. The proposed timing analysis considers floating body effect on the propagation delay for more accurate timing analysis in PD-SOI CMOS circuits. The accuracy of modeling the leakage power in PD-SOI CMOS circuits is improved by considering the interactions between the subthreshold leakage and the gate tunneling leakage, the stacking effect, the history effect, and the fanout effect. The proposed timing and leakage power analysis algorithms are implemented in Matlab, Hspice, and C language. The proposed methodology is applied to ISCAS85 benchmarks, and the results show that the error is within 5% compared with random simulation results.

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Section: Gate Tunneling Leakage Currentmentioning

confidence: 98%

Statistical timing and leakage power analysis of PD-SOI digital circuits

Kim

2008

Analog Integr Circ Sig Process

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“…However, as technology advances, T ox decreases by 30% with every technology generation, and for T ox smaller than 1.4 nm, I Gate rises by about 1000 X in the following process technology step, while I Sub rises by about 5 X under normal scaling theory [7]. An example: NEC's 100 nm process technology has a T ox = 1.6 nm, I Sub of 0.3 n A/µm of gate width, and an NMOS I Gate of 0.65 n A/µm [8]. So, I Gate has already increased to more than double I Sub in some cases.…”

Section: Leakage Sources In Cmos Circuitsmentioning

confidence: 99%

Leakage sources and possible solutions in nanometer CMOS technologies

Elgharbawy

Bayoumi

2005

IEEE Circuits Syst. Mag.

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“…One way to reduce the gate leakage is using high-k dielectrics. There are several high-k materials proposed so far such as oxinitrides (k=4.1) [5], Si 3 N 4 (k=7.8), and HfO 2 (k=25~50) [6]. However, there are many process integration problems with these materials.…”

Section: Introductionmentioning

confidence: 99%

Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage

Bastani

Zukowski

2004

Proceedings of the 14th ACM Great Lakes Symposium on VLSI

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In this paper, we first study the behavior of gate leakage current in a simple inverter. We make some important observations about the gate leakage in both PMOS and NMOS devices. We then study the trade off between power and delay in a standard inverter within a particular buffer chain when reducing the size of the pull-down device. In the last part of this paper, we present an alternate leakage suppressed inverter for driving large loads. We finally compare the performance of our proposed circuit with those of standard and scaled-down inverters and show that we can significantly reduce the standby power in certain situations with a modest reduction in speed.

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A 100 nm node CMOS technology for practical SOC application requirement

Cited by 18 publications

References 0 publications

Statistical timing and leakage power analysis of PD-SOI digital circuits

Statistical timing and leakage power analysis of PD-SOI digital circuits

Leakage sources and possible solutions in nanometer CMOS technologies

Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage

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