A 10 GHz digital amplifier in an ultra-small-spread high-J/sub c/ Nb/Al-AlOx/Nb integrated circuit process

Bhat, A.; Meng, Xiaofan; Whiteley, S.R.; Jeffery, Mark; Duzer, T. Van

doi:10.1109/77.783717

Cited by 22 publications

(7 citation statements)

References 11 publications

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“…A group at the University of California at Berkeley has developed a latching driver that produced a 4-mV output at 10 GHz. They also achieved a low BER of 5 10 at 5 GHz [9]. A driver developed by TRW has produced an output of about 7 mV at 6.2 Gb/s [10].…”

Section: Introductionmentioning

confidence: 95%

High-speed demonstration of an output interface driver for single-flux quantum systems

Harada¹,

Yoshida²,

Yokoyama³

2002

IEEE Trans. Appl. Supercond.

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The high-speed operation of a one-channel output interface for a single-flux quantum (SFQ) system has been demonstrated. The interface consisted of a Josephson latching driver, a room-temperature semiconductor amplifier, and a decision circuit module. The Josephson latching driver was fabricated by using a 2.5-kA/cm 2 standard Nb junction process and used to amplify an SFQ pulse into a 5.5-mV level signal at 10 Gb/s. The interface converted the SFQ pulse signal into a nonreturn-to-zero signal having an amplitude of 1 V at 10 Gb/s.

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Section: Introductionmentioning

confidence: 95%

High-speed demonstration of an output interface driver for single-flux quantum systems

Harada¹,

Yoshida²,

Yokoyama³

2002

IEEE Trans. Appl. Supercond.

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“…These requirements can be observed in latching circuits such as the Manuscript 10 Gb/s latch described in [1], the Suzuki stack [2], [3], and even the HUFFLE [4]. A second classification of circuits, SFQ voltage multipliers [5]- [7], have relevance in the present context.…”

Section: Introductionmentioning

confidence: 99%

Stacked double-flux-quantum output amplifier

Herr

2005

IEEE Trans. Appl. Supercond.

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A suitable data link from RSFQ to semiconductor electronics remains challenging. We report an output amplifier that uses a new pulse multiplier circuit. The pulse multiplier consists of several stages arranged in series; a double-flux-quantum gate at each stage promotes the SFQ pulse to the next stage. Characteristics of the circuit design are: 1) DC power. As with the DFQ gate, every unshunted Josephson junction in the amplifier is loaded by critically-damped junctions that prevent voltage-state modes. 2) Equal rise and fall times that scale with output amplitude. In our case, 50 ps rise and fall time and 1-2 mV output amplitude can be realized, which is ideal for a data rate of 10 Gb/s. 3) Quantum accurate voltage multiplication independent of bias current. 4) Non-return-to-zero (NRZ) operation. The circuit was designed and successfully tested in our 8 kA cm 2 foundry process. A 60 GHz pulse train, generated on-chip, was gated with RSFQ logic to produce a data pattern that was then fed into a pulse multiplier of either ten or twenty stages. Voltage multiplication was observed with operating margins of 21% on bias current. Fast rise time was directly observed; unfortunately, fall time was spoiled by ringing on a 1 ns time scale. It is plausible that small changes to the physical layout of the circuit would produce desired operation.Index Terms-Author, please supply your own keywords or send a blank e-mail to keywords@ieee.org to receive a list of suggested keywords.

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“…For an SS with eight Josephson junctions, a data rate of 10 Gb s −1 was demonstrated with a bit-error-rate (BER) of 1.4×10 −9 [14]. A smaller version with only four Josephson junctions in the stack was operated at the same data rate at a much lower BER of 5 × 10 −12 [15]. Larger stacks tend to operate less stably.…”

Section: Introductionmentioning

confidence: 99%

“…The circuit concept does not well tolerate parameter variations. Thus the SS was even used to qualify the process quality of an excellent low-spread niobium based fabrication process [15]. We describe an in-depth study of several design aspects of the SS to enable its reliable operation in practical applications.…”

Section: Introductionmentioning

confidence: 99%

Design guidelines for Suzuki stacks as reliable high-speed Josephson voltage drivers

Ortlepp

Zheng

Whiteley

et al. 2013

Supercond. Sci. Technol.

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The application of superconducting circuits for high-performance computing and high-speed analog-to-digital converters suffers from the difficulty of amplifying the weak signals of superconducting circuits to the volt level of semiconductor electronics. We refer to the most accepted Josephson circuit used to amplify weak signals of about a millivolt to several tens of millivolts as a Suzuki stack. It can be directly triggered by a single flux quantum pulse and has a very high switching speed of about 25 ps.We report here an in-depth study of design issues for Suzuki stacks with extensive systematic simulations as well as experimental results. We explain the origin of previously reported phenomena such as multiple-level switching, high bit-error-rates, and interactions between stacks, and give design guidance for avoidance of such problems. We show experimental results for a set of Suzuki stacks operating correctly and independently with a single power supply.The presented design guidelines address important characteristics that need to be optimized: output voltage, bias margins, operating frequency, bit-error-rate, delay, power dissipation, and physical size.

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A 10 GHz digital amplifier in an ultra-small-spread high-J/sub c/ Nb/Al-AlOx/Nb integrated circuit process

Cited by 22 publications

References 11 publications

High-speed demonstration of an output interface driver for single-flux quantum systems

High-speed demonstration of an output interface driver for single-flux quantum systems

Stacked double-flux-quantum output amplifier

Design guidelines for Suzuki stacks as reliable high-speed Josephson voltage drivers

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