A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery

Suttorp, Thorsten; Langmann, U.

doi:10.1109/cicc.2007.4405732

Cited by 13 publications

(10 citation statements)

References 10 publications

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“…The eye-opening monitor (EOM) method is widely used for the jitter measurement [16][17][18][19][20]. The horizontal opening time interval is measured in the eye-diagram, and then it is subtracted from the input data period.…”

Section: Proposed Jitter Measurement Schemementioning

confidence: 99%

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An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

Kim¹,

Lim²,

Kim³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20", 30", 40" FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a 0.13 μm process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.Index Terms-Adaptive equalizer, USB 3.0 high-speed receiver, jitter measurement

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Section: Proposed Jitter Measurement Schemementioning

confidence: 99%

“…At every data transition, the upper shift register shifts '1' to the right at the rising edge of dCLK1. After 20 data transitions, the last output (CT [19] (Fig. 5(a)), which finds the optimum equalization coefficient (EQ-CODE) automatically.…”

Section: Jitter Measurement (Jm) Blockmentioning

confidence: 99%

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

Kim¹,

Lim²,

Kim³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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“…For example, Eye-Opening Monitors (EOM) can be constructed to observe signal quality. They are used in [9] for a CTLE equalizer, in [10] for an analog FFE equalizer and in [11] for the adaptation of a CTLE and DFE. In [12], a solution is proposed with asynchronous undersampling histograms to guide an adaptive continuous time linear equalizer (CTLE).…”

Section: Introductionmentioning

confidence: 99%

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

Verplaetse

Keulenaer

Vyncke

et al. 2017

IEEE Trans. Circuits Syst. I

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Abstract-The ever-increasing demand for more efficient data communication calls for new, advanced techniques for high speed serial communication. Although newly developed systems are setting records, off-line determination of the optimal equalizer settings is often needed. Well-known adaptive algorithms are mainly applied for receive-side equalization. However, transmit-side equalization is desirable for its reduced linearity requirements. In this paper, an adaptive sign-sign least mean square equalizer algorithm is developed applicable for an analog transmit-side feed-forward equalizer (FFE) capable of transforming non-return-to-zero modulation to duobinary (DB) modulation at the output of the channel. In addition to the derivation of the update strategy, extra algorithms are developed to cope with the difficult transmit-receive synchronization. Using an analog six tap bit-spaced equalizer, the algorithm is capable of optimizing DB communication of 100 Gb/s over 1.5-m Twin-Ax cable. Both simulations and experimental results are presented to prove the capabilities of the algorithm demonstrating automated determination of FFE parameters, such that error-free communication is obtained (BER< 10 −13 using PRBS9).Index Terms-Duobinary, feed-forward equalizer, analog equalization, adaptive equalization, least mean squares.

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“…In the case that degradation of data eye, due to ISI, is severe, additional decision feedback equalizer (DFE) can be implemented, which can be embedded into the phase detector of CDR. Several other high-speed I/O receiver front-end topologies can be found in [2], [3]. Normally, CTLE will consume huge amount of power at high data rate; therefore, it will be extremely desirable if the CDR can be embedded with equalizer to improve the power efficiency.…”

Section: Introductionmentioning

confidence: 99%

A 25–28Gbps clock and data recovery system with embedded equalization in 65-nm CMOS

Sun

Pan

Wang

et al. 2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

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A novel CDR system with a built-in equalizer for compensating electrical/optical channel loss is presented. A variable-gain delay line is implemented to perform both data delay and equalization simultaneously without consuming extra power. Designed in a 65-nm 1P9M general-purpose CMOS process, the proposed CDR system employs current-mode logic circuits extensively with shunt peaking inductive load to attain the required gain at high speed. To minimize the area occupied by the spiral inductors, custom stacked inductors, achieving an inductance density of 0.3pH/um 2 , are used. The prototype IC occupies less than 0.9mm 2 . Post-layout simulation results show that the CDR is able to recover a 28-Gbps NRZ PRBS data after transmission through a channel with 10-dB loss at 14 GHz when the equalization function is activated. The CDR consumes 100mA from a 1-V supply.

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A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery

Cited by 13 publications

References 10 publications

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

A 25–28Gbps clock and data recovery system with embedded equalization in 65-nm CMOS

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A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery

Cited by 13 publications

References 10 publications

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

Adaptive Transmit-Side Equalization for Serial Electrical Interconnects at 100 Gb/s Using Duobinary

A 25&#x2013;28Gbps clock and data recovery system with embedded equalization in 65-nm CMOS

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A 25–28Gbps clock and data recovery system with embedded equalization in 65-nm CMOS