A 10-bit high speed pipelined ADC

Murshed, Alfakhri M.; Krishna, K. Lokesh; Saif, Marco A.; Anuradha, K.

doi:10.1109/icisc.2018.8399006

Cited by 11 publications

(4 citation statements)

References 9 publications

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“…Also use calibration to reduce the error and use the sub threshold method to reduce the power consumption. 0.18 10 -54.4 19.7 100 0.18 10 69.27 60.52 75 350 (Lv, et al, 2018) 0.5 14 75.51 43.1 136 30 (Murshed, et al, 2018) 0.13 10 -54.7 46.8 200 (Wang, et al, 2017) 0.18 10 62.97 55.58 115 200 (Wang, et al, 2018) 0.018 14 87.1 74.4 120 250 (Li and Du, 2017) 0.018 8 50 45.9 38.9 166 (Fan, et al, 2017) 0…”

Section: Discussionmentioning

confidence: 99%

“…Today Analog signals have been replaced by digital signals. Analog-to-digital convertor (ADC) plays a key role in today's modern telecommunications (Fatemi-Behbahani, et al, 2016, Lv, et al, 2018, Murshed, et al, 2018. The ADC operation is such that the continuous range of the analogue input signal is divided into several sub-ranges and each one of them has a digital code assigned.…”

Section: Introductionmentioning

confidence: 99%

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Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology

Rezapour

Setoudeh

Tavakoli

2019

Journal of Applied Engineering Sciences

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This paper proposed a novel structure of a 10-bit, 400MS/s pipelined analog to digital convertor using 0.18 µm TSMC technology. In this paper, two stages are used to converter design and a new method is proposed to increase the speed of the pipeline analog to digital convertor. For this purpose, the amplifier is not used at the first stage and the buffer is used for data transfer to the second stage, in the second stage an amplifier circuit with accurate gain of 8 that is open loop with a new structure was used to speed up, also the design is such that the first 4 bits are extracted simultaneously with sampling. On the other hand, in this structure, since in the first stage the information is not amplified and transferred to the second stage, the accuracy of the comparator circuit should be high, therefore a new structure is proposed to design a comparator circuit that can detect unwanted offsets and eliminate them without delay, and thus can detect the smallest differences in input voltage. The proposed analog to digital convertor was designed with a resolution of 10 bits and a speed of 400MS/s, with the total power consumption 74.3mW using power supply of 1.8v.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology

Rezapour

Setoudeh

Tavakoli

2019

Journal of Applied Engineering Sciences

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“…Op-amps are among the most widely used electronic devices today, being used in a vast array of consumer, industrial, and scientific devices. Operational Amplifiers, more commonly known as Opamps, are among the most widely used building blocks in Analog Electronic Circuits [4]. Op-amps are linear devices that are ideal for DC amplification and are used often in signal conditioning, filtering or other mathematical operations (add, subtract, integration and differentiation) [5].…”

Section: Imentioning

confidence: 99%

Analysis of Two Stage CMOS Operational Amplifier in 90nm CMOS Technology

Kavya,

Nagasowmya,

Ankitha

et al. 2024

IJRASET

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Operational amplifier circuits are used in computation, instrumentation and other applications. Precision op-amps previously used in instrumentation are now-a-days being used in industrial and automotive applications. Hence, there always exists a need for better precision op-amps. It should operate under a wide temperature range. Nowadays, due to the industry trend of applying standard process technologies to implement both analog circuits and digital circuits on the same chip, Complementary Metal-Oxide Semiconductor (CMOS) technology has become dominant over bipolar technology for analog circuit design in a mixed-signal system. Two-stage Op-Amp is one of the most commonly used Op-Amp architectures. In this work an operational amplifier based on CMOS is presented whose input depends on its bias currents which is 20µA and designed using 180nm and 90nm technologies. In sub-threshold region due to unique behavior of the MOS transistors not only allows a designer to work at low voltages and it also allows operating at low input bias currents. Most CMOS Op-Amps are designed for specific on-chip applications and are only required to drive capacitive loads of a few pf. In this proposed work, design of a two stage fully differential CMOS operational amplifier is presented and simulations are carried out in 180nm and 90nm technologies for various parameters. The simulation is to be carried out using Cadence Virtuoso Tool.

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“…The design procedure and simulation of multistage preamplifiers for use in high speed comparators is explained by W.Shirai et al [8]. A high speed comparator design for use in a 10-bit pipelined ADC is given in [9]. In this proposed work an high speed latched comparator is designed and simulated.…”

Section: Introductionmentioning

confidence: 99%

A High Speed Latched Circuit for Flash ADC

Al-Naamani¹,

Krishna²,

Allabaksh³

et al. 2019

IJITEE

Self Cite

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Practically all electronic systems are realized using integrated circuit(IC) chips. The IC design requires digital signals, but however the physical signals available routinely are either continuous time varying signals or corrupted discrete voltages. These continuous time varying input signals are converted to full voltage swing digital signals by means of a comparator circuit. The comparators use regenerative feedback to transform the output to a full scale digital signal. The core specifications considered in this comparator implementation are power dissipation (PD), propagation delay (tP), output offset voltage and slew rate. The circuit is simulated in CMOS 180nm technology using Tanner EDA tool. The high speed latched comparator circuit is powered with a 1.8V DC power supply and the obtained results show that it operates at 1.67GHz, slew rate is 126 V/µS and the dynamic power dissipation is found to be 0.328mW.

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A 10-bit high speed pipelined ADC

Cited by 11 publications

References 9 publications

Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology

Design an Improved Structure for 10-Bit Pipeline Analog to Digital Converter Based on 0.18µm CMOS Technology

Analysis of Two Stage CMOS Operational Amplifier in 90nm CMOS Technology

A High Speed Latched Circuit for Flash ADC

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