A 10-b, 75-MHz two-stage pipelined bipolar A/D converter

Colleran, W.T.; Abidi, A.A.

doi:10.1109/4.261991

Cited by 66 publications

(8 citation statements)

References 14 publications

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“…This brief studies the harmonic distortion introduced by the differential input adapter [4] placed in front of the array of comparators in flash and folding A/D converters operating without sample and hold. A distributed-constant model of the adapter is proposed, where resistor strings are replaced by r-c lines, following an approach similar to the one suggested in [5] and [6] for the analysis of the transient behavior of the resistive divider used in conventional flash converter.…”

Section: Introductionmentioning

confidence: 99%

Harmonic distortion in high-speed differential A/D converters

Boni

Morandi

1998

IEEE Trans. Circuits Syst. II

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The brief discusses the harmonic distortion introduced by the differential input adapter commonly used in flash and folding A/D converters operating without Sample and Hold. A distributed model of the adapter is proposed, which provides physical insight and allows quantitative evaluation. Moreover, a technique based on a feedforward compensation is presented. It provides a significant reduction of the harmonic distortion with a small increase of the die area.

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Section: Introductionmentioning

confidence: 99%

Harmonic distortion in high-speed differential A/D converters

Boni

Morandi

1998

IEEE Trans. Circuits Syst. II

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“…Successful implementation of folding and interpolation techniques in high-speed A D converters is demonstrated in both bipolar [1]- [4] and, more recently, CMOS technology [5]- [7]. The performance of the A D converters described in these papers makes clear that a folding architecture realizes an optimum balance between power dissipation, clock frequency, and chip area due to the limited number of comparators in this type of A/D converters.…”

Section: Introductionmentioning

confidence: 99%

“…A high folding factor results in a low number of comparators, but on the contrary, it lowers the maximum input signal frequency of the A/D converter. In [4], a folding architecture has been combined with an input track-and-hold amplifier, overcoming this bandwidth limitation in folding A/D converters.…”

Section: Introductionmentioning

confidence: 99%

An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing

Venes

van-de-Plassche

1996

IEEE J. Solid-State Circuits

149

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An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-pm standard digital CMOS technology.

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“…A popular error correction technique used in pipelined ADCs exploits the least significant bit of a "coarse" ADC stage for the error detection and correction. For example, in (Colleran & Abidi, 1993) a 10-bit ADC is constructed by a 4-bit "coarse" and a 7-bit "fine" ADC. The least significant bit of the coarse ADC should match the most significant bit of the fine ADC.…”

Section: Introductionmentioning

confidence: 99%