Harmonic distortion in high-speed differential A/D converters

Boni, Andrea; Morandi, C.

doi:10.1109/82.664250

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Cited by 6 publications

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“…Therefore such subranging solution is not feasible in the GS/s range. The problem has been overcome in the present design using a novel subranging technique based on a couple of dynamic resistive strings [8]. Usually CMOS high-speed ADCs with differential input makes use of a single resistive string providing the required voltage references and dual-differential preamplifiers [9].…”

Section: The Rectifiermentioning

confidence: 99%

Design of a 2-GS/s 8-b Self-Calibrating ADC in 0.18 μ m CMOS technology

Azzolini

Boni

Facen

et al.

2005 IEEE International Symposium on Circuits and Systems

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The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-µm CMOS. A conversion rate as high as 2GS/s with a relatively low power consumption was achieved by means of a couple of interleaved subranging/flash ADCs with a single Track-andHold at the input. Special design solutions were adopted for implementing subranging operation at such a high frequency. Finally, a lower power consumption self-calibrating technique effective for reducing non linearity errors below 1 LSB was implemented.

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Section: The Rectifiermentioning

confidence: 99%