A 1 W CMOS power amplifier for GSM-1800 with 55% PAE

Fallesen, Carsten; Asbeck, P. M.

doi:10.1109/mwsym.2001.967039

Cited by 16 publications

(4 citation statements)

References 6 publications

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“…This result shows that the driver stage successfully delivers square wave signals to the power stage. This amplifier shows the best PAE for wattlevel CMOS PAs published thus far [1], [6]- [8] (see Table I). It demonstrates that the power and efficiency of a CMOS PA are comparable to those of GaAs HBT-based PAs [2].…”

Section: Measurement Resultsmentioning

confidence: 87%

A CMOS RF Power Amplifier Using an Off-Chip Transmision Line Transformer With 62% PAE

Jang¹,

Park²,

Kim

et al. 2007

IEEE Microw. Wireless Compon. Lett.

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In this letter, a two-stage 900-MHz CMOS differential power amplifier (PA) is designed and implemented in a 0.18-m radio frequency CMOS process. A transmission line transformer on a printed circuit board is used as an output power combiner and matching circuits of a class-E power stage. To drive the power stage effectively, cascaded class-D amplifiers are used as driver amplifiers. The PA delivers an output power of 31.7 dBm and a power-added efficiency of 62.4% with a power gain of 30.3 dB, including the losses of the bond-wires and the output transformer.

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Section: Measurement Resultsmentioning

confidence: 87%

A CMOS RF Power Amplifier Using an Off-Chip Transmision Line Transformer With 62% PAE

Jang¹,

Park²,

Kim

et al. 2007

IEEE Microw. Wireless Compon. Lett.

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“…The theoretical efficiency of the Class AB PA is about the efficiency of Class A (50%) and Class B (78.5%). The practical efficiency of CMOS Class AB PA achieved is about 55% [4].…”

Section: Class Ab Pamentioning

confidence: 98%

Energy efficiency in CMOS power amplifier designs for ultralow power mobile wireless communication systems

Mariappan¹,

Rajendran²,

Noh³

et al. 2020

Turk J Elec Eng & Comp Sci

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Wireless communication standards keep evolving so that the requirement for high data rate operation can be fulfilled. This leads to the efforts in designing high linearity and low power consumption radio frequency power amplifier (RFPA) to support high data rate signal transmission and preserving battery life. The percentage of the DC power of the transceiver utilized by the power amplifier (PA) depends on the efficiency of the PA, user data rate, propagation conditions, signal modulations, and communication protocols. For example, the PA of a WLAN transceiver consumes 49% of the overall efficiency from the transmitter. Hence, operating the PA with minimum power consumption without trading-off the linearity is vital in order to achieve the goal of fully integrated system-on-chip (SoC) solution for 4G and 5G transceivers. In this paper, the efficiency in CMOS PA is discussed through the review of multifarious efficiency enhancement techniques in CMOS PA design. This is categorized into the review of efficiency in fundamental classes of PA in which Class E achieves the highest efficiency of 67%, followed by complex architectures utilized to enhance the efficiency level of the PA in which the outphasing architecture achieved the highest efficiency of 60.7%.

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“…Obtaining similar results using CMOS has been a more difficult task. Nevertheless, improvements in the technology and in modeling have increased the efficiency, with recent values reaching 55% [5]. At a slightly lower frequency a value of 62% has been published [6].…”

Section: The High-voltage Class E Amplifiermentioning

confidence: 99%

Design of a Class E Power Amplifier with LDMOS in Standard CMOS

Ramos

Steyaert

2005

Analog Integr Circ Sig Process

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This paper describes the development of a high-voltage transistor in a standard 0.35 µm CMOS technology and its application on a class E power amplifier for mobile communications. The use of a higher voltage already available in the battery has the benefit of reducing the electromigration constrains and having lower voltage drops in the interconnects due to the use of a lower current.Measured results on the active device and simulation show that is possible to achieve a higher power added efficiency using a lateral double diffused MOS, while reducing the current draining the battery.

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A 1 W CMOS power amplifier for GSM-1800 with 55% PAE

Cited by 16 publications

References 6 publications

A CMOS RF Power Amplifier Using an Off-Chip Transmision Line Transformer With 62% PAE

A CMOS RF Power Amplifier Using an Off-Chip Transmision Line Transformer With 62% PAE

Energy efficiency in CMOS power amplifier designs for ultralow power mobile wireless communication systems

Design of a Class E Power Amplifier with LDMOS in Standard CMOS

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