A 1-V 8-bit 0.95mW successive approximation ADC for biosignal acquisition systems

Lee, Shuenn-Yuh; Cheng, Chun‐Yu; Wang, Cheng-Pin; Lee, Shyh-Chyang

doi:10.1109/iscas.2009.5117832

Cited by 23 publications

(5 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Despite none of the circuits were optimized for speed, matching, or power efficiency, very low FOM of 280 fJ/conv.-step was attained. Comparing with recently published SAR ADC designs [20][21][22][23][24] supply boosted SAR ADC achieves; smallest layout footprint, lowest power consumption, and reasonable FOM as shown on the Table 3. Normalized areas of the designs were determined by dividing the reported design areas with the minimum gate area (1.5 * L min 2 ) of the process in use and normalized further with the minimum one which is our design.…”

Section: Resultsmentioning

confidence: 86%

“…This FOM shows that supply boosting technique does not degrade the energy efficiency of circuits. We have to also note that this FOM is achieved without doing any circuit or architectural improvement on standard SAR ADC topology chosen, and unlike the recently reported SAR ADCs [17][18][19][20][21][22][23][24] a mature 0.5 lm CMOS technology with high-Vt devices was used.…”

Section: Measurement Resultsmentioning

confidence: 99%

See 1 more Smart Citation

A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

2010

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

This paper presents a new very low-power, low-voltage successive approximation analog to digital converter (SAR ADC) design based on supply boosting technique. The supply boosting technique (SBT) and supply boosted (SB) circuits including level shifter, comparator, and supporting electronics are described. Supply boosting provides wide input common mode range and sub-1 Volt operation for the circuits designed in standard CMOS processes that have only high-V t MOSFETs. A 10-bit supply boosted SAR ADC was designed and fabricated in a standard 0.5 lm, 5 V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are ?0.8 and -0.9 V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.04, power consumption of 147 nW with sampling rate of 1.0 KS/s on 1 Volt supply. Measured figure of merit (FOM) was 280 fJ/ conversion-step. Proposed supply boosting technique improves input common mode range of both SB comparator and SAR ADC, allows sub-1 Volt operation when threshold voltages are in the order of the supply voltage, and achieves low energy operation. Thus, SBT is suitable for mixed-signal circuit designed for energy limited applications and systems in where supply voltage is in the order of threshold voltages of the process.

show abstract

Section: Resultsmentioning

confidence: 86%

Section: Measurement Resultsmentioning

confidence: 99%

A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

2010

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

show abstract

“…In 2003, Sauerbrey et al [9] described a device with power consumption of 0.85 μW for 8-bit sampling at 4 kS/s. More recently, similar power levels have been achieved at 10 kS/s [10]. More functional processing can also be done at low power; in [11] a systemon-chip for biosignal processing is reported with average power consumption of 20 μW per bio-sensing node, and this includes analog amplification, digitisation and some digital signal processing.…”

Section: Sensor Node Power Requirementsmentioning

confidence: 85%

Energy Harvesting and Power Delivery

Yeatman

Mitcheson

2014

Body Sensor Networks

View full text Add to dashboard Cite

As we have seen in previous chapters, the increasing miniaturisation and cost reduction of sensors, circuits and wireless communication components is creating new possibilities for networks of wireless sensors, in wearable and other applications. However, in order for sensors to be wireless, or untethered, this requires not only wireless communication to and from the nodes, but also wireless powering. Batteries, of course, provide this capability in the great majority of portable electronic devices, and thus are the obvious solution also for the wireless sensor node application. However, their need for replacement or recharging introduces a cost and convenience penalty which is already undesirable in larger devices, and is becoming increasingly unacceptable for sensor nodes as the number of these (their ubiquity) grows. As an alternative, therefore, sources which harvest energy from the environment are very attractive. At the same time, the power demands of many electronic functions, wireless communication being a particularly important example in this context, are continuously falling. Although this lightens the demands for batteries, it also makes alternatives based on energy harvesting look more and more realistic.Where batteries can power a sensor node for its whole expected lifetime without maintenance, and without dominating the node cost or weight, this is likely to remain the favoured solution in most cases, although even there, energy harvesting methods have advantages to offer. The materials required in batteries are often toxic or environmentally unfriendly, adding to the burden of both bio-compatibility for implanted use and to the end-of-life disposal. Where a lifetime beyond what a battery can provide is needed, the "eternal" nature of the harvesting supply clearly becomes particularly favourable.

show abstract

“…The detailed circuit components are as follows. (1) Preamplifier: Avariable gain amplifier (VGA) with automatic gain control (AGC) circuits composed of a peak detector (PD), and a nonlinear controller (NC) for digital ECG [30] (2) Low pass filter [31] (3) AD Converter [32].…”

Section: Rfid Integratationmentioning

confidence: 99%

Integrated successive approximation register analog-to-digital converter for healthcare systems applications

Lai

Huang

et al. 2014

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

View full text Add to dashboard Cite

This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. The proposed a 1-V 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. By applying SAR control logic that reduces half comparator and digital circuit power consumption, the provided SAR ADC achieves low power consumption. Measured results show that at the supply voltage of 1.0 V and sampling rate of 2 MS/s, the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 49.8 dB, a signal-to-noise and distortion ratio (SNDR) of 44.8 dB, an effective number of bits (ENOB) of 7.15 bits, a differential nonlinearity (DNL) of 0.39 LSB, an integral nonlinearity (INL) of 1.6 LSB and a power consumption of 40.2 µW.

show abstract

A 1-V 8-bit 0.95mW successive approximation ADC for biosignal acquisition systems

Cited by 23 publications

References 7 publications

A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

Energy Harvesting and Power Delivery

Integrated successive approximation register analog-to-digital converter for healthcare systems applications

Contact Info

Product

Resources

About