A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization

Kneip, Adrian; Lefebvre, Martin; Verecken, Julien; Bol, David

doi:10.1109/esscirc55480.2022.9911348

Cited by 4 publications

(5 citation statements)

References 9 publications

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“…Color versions of one or more of the figures in this article are available online at http://ieeexplore.ieee.org E datasets (such as CIFAR100, CIFAR10, and MNIST) [13,21,22]. However, some CNN-based industrial applications demand a reasonable classification accuracy on the ImageNet dataset [23].…”

Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

“…Inference of widely-used classification CNNs requires signed (or unsigned) format and signed format for data and weights, respectively [26]; signed format for both data and weights is usually needed for a finite impulse response (FIR) filter [5]; unsigned format for both data and weights is appropriate for Gaussian image filtering to gain higher accuracy compared with signed format with the same bit widths [27]. Some previous works have achieved bit-flexible convolution layers with signed/unsigned weights and unsigned inputs by assigning negative factors to the sign-bit CIM columns [13,21,22]. Saurabh Jain et al attempted to implement convolution layers with signed inputs/weights in SRAM-CIM using duplicated word lines, which cannot achieve flexible bit-width of weights.…”

Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

“…Different from the SBIPW strategy, each 𝑞 is the combination of one or several 𝑦 , . The relationship is shown in (13).…”

Section: ) Serial Bit Input Parallel Weightmentioning

confidence: 99%

“…However, the incompatibility of the SRAM-CIM operator adversely affects the hardware efficiency of SRAM-CIM-based accelerators [12]. Unlike the flexible digital-based MAC unit, the SRAM-CIM macros introduce programming difficulty for convolution mapping with rectangle-shaped MAC arrays with side lengths ranging from 64 to 1024 [12,13]. Although several approaches have been proposed to optimize the weight-level mapping in RRAM-CIM macros, such as SDK [14] and VW-SDK [15], high-degree weight-level parallelism can lead to the presence of spare cells within the macros.…”

Section: Introductionmentioning

confidence: 99%

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A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

Bai,

Li,

Zhang

et al. 2024

Preprint

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Deploying convolution-based algorithms into SRAM computing-in-memory (CIM) systems faces various challenges, such as operator incompatibility and intrinsic non-ideal error. This paper proposes a compilation framework to address this issue. Efficient weight mapping strategies are introduced to improve the utilization of SRAM-CIM macro. The intrinsic non-ideal errors of SRAM-CIM macro are also taken into consideration, and two efficient error correction schemes are proposed, which include calibration of computation voltage linear error (CCVLE) and the mitigation of analog-to-digital quantization error (MAQE). In addition, bit-width flexibility and signed-unsigned reconfigurability are also supported to facilitate the deployment of various convolution-based algorithms. ResNet18, finite impulse response (FIR) filtering, and Gaussian image filtering are deployed into a multi-macro SRAM-CIM system. These algorithms serve as deployment representatives of convolutional neural network (CNN), digital signal processing (DSP), and digital image processing (DIP), respectively. The results show that the introduced weight mapping strategies improve the macro utilization by 63.29% and 21.10% for two types of frequently used convolution layers compared to the traditional strategy. Moreover, the proposed error correction schemes achieve similar algorithm accuracy to the floating-point results, and the deployment result of ResNet18 achieves 66.3%~70.1% top-1 classification accuracy evaluated on the ImageNet dataset with different throughput tradeoffs.

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Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

Section: (C) Most Previous Work Evaluate Cnns On Lightweightmentioning

confidence: 99%

“…Different from the SBIPW strategy, each 𝑞 is the combination of one or several 𝑦 , . The relationship is shown in (13).…”

Section: ) Serial Bit Input Parallel Weightmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

Bai,

Li,

Zhang

et al. 2024

Preprint

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“…Another field which shows their advantage is sparse lightweight networks [15], [16], a main category under neural networks. In contrast to digital SRAM-based CIMs, which trade more area and computing time for higher precision [17], [18], [19], [20], analog-mixedsignal SRAM-based CIMs perform small kernel convolution computations in a single cycle, significantly reducing computation time at the cost of minor recognition rate lost [21], [22], [23]. The lightweight network's high parallelism and energy efficiency computing requirements when using small convolution kernels, as well as its high tolerance for computational accuracy, perfectly match the characteristics of analog in-memory computing.…”

Section: Introductionmentioning

confidence: 99%

A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks

Gu,

Dou,

You

et al. 2024

IEEE Access

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In this paper, we present an analog-mixed-signal 6T SRAM computing-in-memory (CIM) macro. The macro uses dual-wordline 6T bitcells to reduce power consumption and write-disturb issues. The macro also proposes an analog computation logic circuit for high precision, energy efficient charge-domain computation. The bitcell structure combined with the analog computation logic circuit allows direct input of signed activations and weights to the chip for full signed computation. The proposed macro consists of four CIM blocks, each with four 32x8 compute blocks, a pulse generator, an analog computation logic circuit and a SAR-ADC. Fabricated in a 55 nm process, our CIM macro test chip achieves an energy efficiency of 7.3 TOPS/W. A comprehensive computing test that encompasses the entire range of inputs and weights has been conducted. The results show that the CIM macro test chip can achieve a precision of 79.51% in a 1-FE error range of 71.88%. The target application of the proposed CIM macro is lightweight neural networks, this is demonstrated by mapping a pre-trained network into the macro and achieving a recognition accuracy of 92.28% on the CIFAR-10 dataset. The design surpasses existing designs in comprehensive consideration of energy efficiency, technology and bit width. Computing-in-memory, SRAM, dual-wordline, neural network, charge-domain, multiplyand-accumulate INDEX TERMS

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A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices

Zhou,

Wei

et al. 2024

IEEE Trans. Circuits Syst. I

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A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization

Cited by 4 publications

References 9 publications

A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

A Compilation Framework for SRAM Computing-in-Memory Systems with Optimized Weight Mapping and Error Correction

A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks

A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices

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