A 1-Kbit EEPROM in SIMOX technology for high-temperature applications up to 250/spl deg/C

Gogl, D.; Fiedler, H. L.; Spitz, Martin; Parmentier, Brigitte

doi:10.1109/4.871314

Cited by 11 publications

(3 citation statements)

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“…The intrinsic carrier concentration is proportional to temperature due to the decreased bandgap. Therefore, devices with higher bandgap are preferred for high temperature applications to suppress the amount of leakage at the cost of additional process steps [1], [5], [6]. In addition, SOI technology has been widely accepted for high temperature operation [4].…”

Section: Design Challenges In Low Power Srams For High Temperature Applicationsmentioning

confidence: 99%

“…The development of ruggedized electronics such as automotive, aerospace and Logging-While-Drilling (LWD) systems has demanded more robust integrated circuit solutions with reliable operation at high temperatures (> 200C) [1]- [4]. One of the most challenging issues in circuit design for high temperature operation is leakage, which increases exponentially with temperature.…”

Section: Introductionmentioning

confidence: 99%

“…However, there have been very few memory solutions offering reliable operation up to 300C except EEPROMs. Gogl et al presented an EEPROM with the operating temperature up to 250C with the aid of SIMOX technology [1], [5]. In [4], Grella et al experimentally demonstrated that EEPROMs can operate up to 400C even though the threshold voltage window and the storage time are degraded dramatically.…”

Section: Introductionmentioning

confidence: 99%

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Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C

Kim

2014

IEEE J. Solid-State Circuits

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This paper presents an 8-Kbit low power SRAM for high temperature (up to 300C) applications. For reliable low voltage operation, we employed a decoupled 8T SRAM cell structure. To minimize the performance variations caused by the wide operating temperate range, supply voltage is selected in the near-threshold region. A temperature-aware bitline sensing margin enhancement technique is proposed to mitigate the impact of significantly increased bitline leakage on bitline swing and sensing window. A temperature-tracking control circuit generates bias voltage for optimal pull-up current for realizing the proposed enhancement technique. Test chips were fabricated in a commercial 5 V, 1.0-µm SOI technology. Test chip measurement demonstrates successful operation down to 2 V at 300C. The average energy of 0.94 pJ was achieved at 2 V and 300C.

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Section: Design Challenges In Low Power Srams For High Temperature Applicationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%