A 1-GSample/s, 15-GHz Input Bandwidth Master–Slave Track-and-Hold Amplifier in InP DHBT Technology

Bouvier, Y.; Ouslimani, A.; Konczykowska, A.; Godin, J.

doi:10.1109/tmtt.2009.2033252

Cited by 21 publications

(6 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Because the goal THA is used in ultra-high-speed ADC, to reduce the influence of feedback circuit in sampling speed, open-loop structure [1][2][3][4] shown in Fig.1 is adopted to realized ultra-high-speed request.…”

Section: Open-loop Structure Of Thamentioning

confidence: 99%

Circuit design of Track-And-Hold Amplifier in Ultra-High-speed Folding-Interpolating ADC

Liu¹,

Wang²,

Ding³

2016

Proceedings of the 2016 6th International Conference on Machinery, Materials, Environment, Biotechnology and Computer

View full text Add to dashboard Cite

Among the designs of ultra-high-speed analog to digital converter, folding-interpolating structure has great advantages in control of chip area and power dissipation. But the frequency-doubled effect of folding-interpolating ADC will restrict dynamic performances of ADC, such as bandwidth and linearity, etc. However, introducing Track-And-Hold Amplifier(THA) into folding-interpolating ADC can ease these shortages effectively, and thus improve dynamic performances of ADC. The structure of THA adopts open-loop structure, which could help realize the request of high speed without the influence of feedback circuit. To improve the circuit linearity, the input buffer adopts open-loop linearization technology and the output buffer adopts method of compensation and cancellation. Sampling switch also choose switch emitter follower sampling switch with greater dynamic performances. By introducing feed-through compensation capacitance, the input signal and hold signal can be completely separated, which could also help improve dynamic performances of circuit. Finally, the designed THA is taken a simulation with 3GHz clock frequency and 500MHz input frequency. The results of the simulation show that the THA can keep great dynamic performances even in ultra-high clock frequency, which lays solid foundation for further design of ultra-high-speed folding-interpolating ADC.

show abstract

Section: Open-loop Structure Of Thamentioning

confidence: 99%

Circuit design of Track-And-Hold Amplifier in Ultra-High-speed Folding-Interpolating ADC

Liu¹,

Wang²,

Ding³

2016

Proceedings of the 2016 6th International Conference on Machinery, Materials, Environment, Biotechnology and Computer

View full text Add to dashboard Cite

show abstract

“…The prototype is implemented in 2-µm GaAs HBT technology. Although many high-speed high linearity THAs have been reported using InP, SiGe and advanced CMOS process [7,8,9,10], GaAs HBT has a number of advantages for fast THA circuits, such as high g m , good V BE matching and commercial maturity. This work detailed the circuit design and measurements of a high linearity 8 GSa/s sampling rates GaAs HBT MMIC THA for future high-speed ADC used in direct conversion receivers.…”

Section: Introductionmentioning

confidence: 99%

A high linearity, 8-GSa/s track-and-hold amplifier in GaAs HBT technology

Zhang

et al. 2018

IEICE Electron. Express

View full text Add to dashboard Cite

A high linearity full differential 8 GSa/s track-and-hold amplifier (THA) is presented in this paper. The proposed THA is designed and implemented using 2-µm GaAs HBT technology to be targeted for faster operation in sampling systems at a clock frequency of GHz. In this THA, an alternative switch emitter follower (SEF) is used as a switching stage with a Schottky diode for hold-mode isolation enhancement and high-speed operation. In conjunction with well-designed input buffer allows us to achieve high linearity and comparable dynamic performance. Measured small signal −3 dB bandwidth, and hold-mode isolation are better than 3.6 GHz and 40 dB, respectively. The prototype achieves a spurious-free dynamic range (SFDR) of 43.9 dB at 0.5 GHz and an average total harmonic distortion (THD) below −40 dBc up to a first Nyquist frequency of 4 GHz. This work has the potential for wideband, high speed and low distortion analog to digital converter (ADC) used in the future direct sampling systems.

show abstract

“…The paper introduces a THA architecture whose core is a SEF sampling scheme which is the preferred choice when high sampling rates (f s [ 0.5GS/s) in conjunction with medium-to-high resolution performances (C8 bit) are required [7][8][9][10][11][12][13][14][15]. The proposed THA allows to increase the ENOB at high sampling rates.…”

Section: Introductionmentioning

confidence: 99%

A 12-bit track and hold amplifier for giga-sample applications

Cannone

Avitabile

2015

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

The paper presents a track-and-hold amplifier (THA), based on the switched emitter follower topology, suitable for emerging receivers architectures and data acquisition systems. The THA exploits four concurrent techniques, all described in the paper, which allow to reduce the hold-mode feedthrough; to attenuate the differential droop rate; to improve the linearity of the input buffer; and to optimize the third order harmonic distortion for RF sampling operation. The effectiveness of this novel approach is demonstrated using a low cost 0.35 lm SiGe technology. The THA core draws about 145 mA from 3.5 V supply. The THA provides a spurious-free dynamic range (SFDR) better than 72 dB when it is used for sampling an incoming signal of 0.9 V pp centered around 925 MHz at a sampling rate of 0.5 GS/s. The THA allows a max sampling frequency equal to 6 GS/s and a max input frequency equal to 2.5 GHz and provides a SFDR better than 50 dB in all the available working conditions.

show abstract

A 1-GSample/s, 15-GHz Input Bandwidth Master–Slave Track-and-Hold Amplifier in InP DHBT Technology

Cited by 21 publications

References 8 publications

Circuit design of Track-And-Hold Amplifier in Ultra-High-speed Folding-Interpolating ADC

Circuit design of Track-And-Hold Amplifier in Ultra-High-speed Folding-Interpolating ADC

A high linearity, 8-GSa/s track-and-hold amplifier in GaAs HBT technology

A 12-bit track and hold amplifier for giga-sample applications

Contact Info

Product

Resources

About