A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem

Borgatti, M.; Call, L.; Sandre, G. De; Foret, B.; Iezzi, D.; Lertora, F.; Muzzi, G.; Pasotti, M.; Poles, M.; Rolandi, P.L.

doi:10.1109/isscc.2003.1234203

Cited by 9 publications

(4 citation statements)

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“…Table 1 We then estimate FLASH and SRAM memory area. FLASH densities have increased drastically, varying from 1MB/mm 2 for the slower NAND FLASH memories, to 128KB/mm 2 for randomaccess NOR FLASH memories [13]. We use the more conservative estimate, obtaining an area of 0.625 mm 2 for all eight blocks.…”

Section: Area Estimationmentioning

confidence: 99%

Hardware speech recognition for user interfaces in low cost, low power devices

Nedevschi

Patra

Brewer

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user interfaces as part of an effort to bring Information and Communication Technologies (ICTs) to underdeveloped regions of the world.Our system architecture exploits a shared infrastructure model. The computationally intensive task of speech model training and retraining is performed offline by shared servers, while the actual recognition of speech is conducted on low-cost hand-held devices using custom hardware.The recognizer is extremely flexible and can support multiple languages or dialects with speaker-independent recognition.Dynamic loading of speech models is used for changing language grammar and retraining, while reprogramming is used to support evolution of recognition algorithms. The focus on small sets of words (at one time) reduces the complexity, cost and power consumption. We design the speech decoder, the central component of the recognizer, and we validate it via a prototype FPGA implementation. We then use ASIC synthesis to estimate power and size for the design.Our evaluations demonstrate an order of magnitude improvement in power compared with optimized recognition software running on a low-power embedded general-purpose processor of the same technology and of similar capabilities. The synthesis also estimates the area of the design to be about 2.5mm 2 , showing potential for lower cost. In designing and testing our recognizer we use datasets in both English and Tamil languages.

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Section: Area Estimationmentioning

confidence: 99%

Hardware speech recognition for user interfaces in low cost, low power devices

Nedevschi

Patra

Brewer

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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“…Configurable processors (like Arc or Tensilica) are one possible means to achieve processor specialization from a RISCbased platform. Reconfigurable processors take this one step further, by allowing run-time changes to the architecture [4].…”

Section: Heterogeneous Multi-processorsmentioning

confidence: 99%

“…• The development and manufacturing of a 1 GOPS reconfigurable signal processing IC [4]. This combines a commercial configurable RISC core with an embedded FPGA fabric which implements the application-specific instruction extensions.…”

Section: Current Activities and Outlookmentioning

confidence: 99%

System-on-chip beyond the nanometer wall

Magarshack

Paulin

2003

Proceedings of the 40th Annual Design Automation Conference

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In this paper, we analyze the emerging trends in the design of complex Systems-on-a-Chip for nanometer-scale semiconductor technologies and their impact on design automation requirements, from the perspective of a broad range SoC supplier.We present our vision of some of the key changes that will emerge in the next five years. This vision is characterized by two major paradigm changes. The first is that SoC design will become divided into four mostly non-overlapping distinct abstraction levels. Very different competences and design automation tools will be needed at each level.The second paradigm change is the emergence of domain-specific S/W programmable SoC platforms consisting of large, heterogeneous sets of embedded processors. These will be complemented by embedded reconfigurable hardware and networks-on-chip. A key enabler for the effective us of these flexible SoC platforms, is a high-level parallel programming model supporting automatic specification-to-platform mapping.

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“…Thus, ENFIRE operates in a spatio-temporal manner, which can be optimized to provide high energy efficiency for a given application. This represents a paradigm shift toward more balanced energy-efficient computing that can serve as either a stand-alone FPGA replacement or as an on-die integrated solution within a CPU leading to increased flexibility, dynamic reprogrammability, and efficient use of the die area for a variety of workloads [14], [15], including fine-grained and energy-efficient FPGA-like logic functions. In addition, we have developed a custom application mapping tool to efficiently map applications into the ENFIRE framework.…”

Section: Introductionmentioning

confidence: 99%

ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware

Qian

Babecki

Karam

et al. 2017

IEEE Trans. VLSI Syst.

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Field programmable gate arrays (FPGAs) are well-established as fine-grained reconfigurable computing platforms. However, FPGAs demonstrate poor scalability in advanced technology nodes due to the large negative impact of the elaborate programmable interconnects (PIs). The need for such vast PIs arises from two key factors: 1) fine-grained bit-level data manipulation in the configurable logic blocks and 2) the purely spatial computing model followed in the FPGAs. In this paper, we propose ENFIRE, a novel memory-based spatio-temporal framework designed to provide the flexibility of reconfigurable bit-level information processing while improving scalability and energy efficiency. Dense 2-D memory arrays serve as the main computing elements storing not only the data to be processed but also the functional behavior of the application mapped into lookup tables. Computing elements are spatially distributed, communicating as needed over a hierarchical bus interconnect, while the functions are evaluated temporally inside each computing element. A custom software framework facilitates application mapping to the framework. By leveraging both spatial and temporal computing, ENFIRE significantly reduces the interconnect overhead when compared with FPGA. Simulation results show an improvement of 7.6× in energy, 1.6× in energy efficiency, 1.1× in leakage, and 5.3× in unified energy efficiency, a metric that considers energy and area together, compared with comparable FPGA implementations.Index Terms-Energy efficiency, field programmable gate arrays (FPGA), fine-grain reconfigurable hardware, memorybased computing (MBC), spatio-temporal computing. Manuscript

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A 1 GOPS reconfigurable signal processing IC with embedded FPGA and 3-port 1.2 GB/s flash memory subsystem

Cited by 9 publications

References 1 publication

Hardware speech recognition for user interfaces in low cost, low power devices

Hardware speech recognition for user interfaces in low cost, low power devices

System-on-chip beyond the nanometer wall

ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware

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