A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

Matano, T.; Takai, Y.; Takahashi, Toshihiko; Sakito, Y.; Takaishi, Y.; Fujisawa, Hironori; Kubouchi, S.; Narui, S.; Arai, K.; Morino, Mario; Nakamura, M.; Miyatake, S.; Sekiguchi, Toshio; Koyama, K.; Miyazawa, K.

doi:10.1109/vlsic.2002.1015058

Cited by 14 publications

(3 citation statements)

References 3 publications

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“…It consists of two DFFs and a dummy delay. The propagation delay from to is (7) where and are the clock-to-delay and the reset-to-delay, respectively, of the DFF, and is the delay of an inverter. The dummy delay is realized by the same DFF and a transmission gate with the same size as the inverter.…”

Section: Edge Combinermentioning

confidence: 99%

“…A 50% duty cycle is often required in double-edge-triggered applications. The dual-loops architecture [7] and the complementary dual-structures [11], [13] are often adopted to realize the duty cycle requirement but the hardware overhead is almost double. The setting/resetting architecture [12] with an edge combiner achieves 50% duty cycle by using single delay line.…”

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confidence: 99%

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A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

Yang

Liu

2007

IEEE J. Solid-State Circuits

136

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A wide-range all-digital delay-locked loop (ADDLL) is presented to achieve low jitter, low power and process immunity. The variable successive approximation register-controlled algorithm is proposed to eliminate the harmonic-locking issue in wide-range operation. It can also achieve the fast-locking property and closed-loop operation. With the balanced edge combiner, the ADDLL outputs a synchronous clock with the duty cycle close to 50% when the duty cycle of the input clock varies from 20% to 80%. Fabricated in 0.18 m CMOS technology, the ADDLL maintains a fixed one input clock cycle latency from 40 MHz to 550 MHz without the harmonic-locking issue. It dissipates 12.6 mW from a 1.8 V supply at 550 MHz. The measured root-mean-square and peak-to-peak jitters at 550 MHz are 1.5 ps and 12 ps, respectively.

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Section: Edge Combinermentioning

confidence: 99%

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confidence: 99%

A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

Yang

Liu

2007

IEEE J. Solid-State Circuits

136

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“…Most of the calibration techniques for up to 1.6 Gbps memory interfaces and SDRAMs deal mainly with output impedance and on-die termination adjustment [1][2][3] techniques, whereas there are only few reported works addressing Data Strobe (DQS) masking and bit deskew [4][5][6][7][8][9] issues. In this work, we present a combined implementation of three different calibration mechanisms (DQS strobe, bit deskew and I/O calibration) in the same memory physical interface using novel, advanced and dynamic techniques for each separate calibration scheme.…”

Section: Introductionmentioning

confidence: 99%

Advanced calibration techniques for high-speed source–synchronous interfaces

Plessas¹,

Alexandropoulos²,

Koutsomitsos³

et al. 2011

IET Comput. Digit. Tech.

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Advanced and dynamic calibration techniques for maximising the link performance of parallel source -synchronous interfaces are introduced and demonstrated in this study, using as a case study a 533 MHz DDR2 SDRAM memory interface implemented in 90 nm standard complementary metal-oxide-semiconductor (CMOS), whereas most of them have been validated at 800 MHz too. A novel dynamic strobe masking system (DSMS) has also been employed which, in contrast to traditional techniques, adjusts dynamically the length of the masking signal in real time, based on the incoming strobe. Furthermore, optimal data capture is achieved by employing a fast bit-deskew calibration engine, while also a novel I/O calibration scheme is included. Post-layout simulation results demonstrate that the dynamic calibration and skew compensation techniques employed improve the timing margin while providing advanced robustness over process, voltage and temperature variations.

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Clock Partitioning and Skew Control

Clock Generators for SOC Processors

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A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

Cited by 14 publications

References 3 publications

A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm

Advanced calibration techniques for high-speed source–synchronous interfaces

Clock Partitioning and Skew Control

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