A 1.99-ns 0.5-pJ Wide Frequency Range Level Shifter With Closed-Loop Negative Feedback

Karimi, Mousa; Ali, Mohamed; Hassan, Ahmad; Weber-Boisvert, Guillaume; Abuelnasr, Ahmed; Gosselin, Benoît

doi:10.1109/newcas49341.2020.9159830

Cited by 6 publications

(5 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally, VA is amplified through two inverters to buffer the signal and to generate VDDH. The design of the level shifter was summarized in a conference paper [7]. Compared to [7], this paper presents a detailed description of the design, and provide the measurement results obtained with the fabricated chip, which were not available in [7].…”

Section: Proposed Ls Architecture and Operationmentioning

confidence: 99%

“…The design of the level shifter was summarized in a conference paper [7]. Compared to [7], this paper presents a detailed description of the design, and provide the measurement results obtained with the fabricated chip, which were not available in [7]. Detailed design explanations and a mathematical analysis of the circuit are also provided to fully cover the operation of the presented circuit.…”

Section: Proposed Ls Architecture and Operationmentioning

confidence: 99%

“…The proposed LS is allowed to work only during the PD; therefore, the integral bounds of ( 6) are from t0 to t0+tpr, where t0 indicates the exact start time of the LS input signal (IN) going up and t0+tpr indicates the moment that VA reaches VM. Thus, replacing VA by VM in (6) and evaluating this integral over the rising PD tpr yields (7) Which can be approximated using Simpson's rule (8) Replacing dt by a time interval ∆t in (3) yields (9) where ∆𝑉 𝐴 is the variation of VA over the time interval ∆t. The value of Cp is determined by (10) In (10), the value of iSDMP2 depends on the region of operation of MP2.…”

Section: Cdmp4=cdsmp4+cdgmp4mentioning

confidence: 99%

“…Level shifters (LSs) are key circuits in numerous microelectronic systems including systems-on-chip (SoCs) and complex system-in-package (SiP) devices [1]- [4]. These circuits are used to translate one signal level to another, allowing signals to be properly transferred across different supply voltage domains [5]- [7]. High-performance telecommunication systems require high-speed LS circuits consuming as low power as possible.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

et al. 2022

View full text Add to dashboard Cite

A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 µm CMOS technology occupies a silicon area of only 25 µm×25 µm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, VDDL=0.8 V, and a capacitive load of CL=0.1 pF.

show abstract

Section: Proposed Ls Architecture and Operationmentioning

confidence: 99%

Section: Proposed Ls Architecture and Operationmentioning

confidence: 99%

Section: Cdmp4=cdsmp4+cdgmp4mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

et al. 2022

View full text Add to dashboard Cite

show abstract

“…These DDPLs are illustrated in Fig. 13 (a) with different colors and names (A, B, C, D, E, and F) [43]- [45]. Given a convenient amount of dead-time, losses A and B in the half-bridge circuit are totally eliminated, and the volumes of C-F are greatly minimized (Fig.…”

Section: B Validation With Half-bridge Circuitmentioning

confidence: 99%

An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

Karimi

Ali

Hassan

et al. 2022

IEEE Trans. Circuits Syst. I

Self Cite

View full text Add to dashboard Cite

In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of halfbridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35 µm technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of 70 µm × 180 µm. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40% drop in power losses in the half-bridge circuit.

show abstract

A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications

Karimi

Ali

Hassan

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

A novel level down shifter intended for translation of signals with different amplitudes in System-on-Chip (SoC) applications is presented. This new single supply down-shifter architecture, implemented in a 0.35-µm AMS CMOS technology provides multiple reconfigurable levels. A diode connected circuit structure, a current source, five transmission gates, a diodesupercapacitor combination, and input/output buffers are employed to implement this reconfigurable level shifter. The circuit receives a pulse shaped signal with an amplitude of 3.3 V, and provides three different signals with nominal amplitudes of 1.2 V, 1.8 V, and 2.5 V depends on the circuit configuration. The proposed circuit successfully drives a range of capacitive loads between 10 fF and 350 pF. The presented circuit consumes a static and a dynamic power consumptions of 62.37 pW and 108.9μW, respectively from a 3.3V supply, at an operating frequency of 1 MHz and a capacitive load of 10 pF. Post-layout simulation results show that the fall and rise propagation delays of the three configurations are in the range of 0.54 ns-26.5 ns and 11.2 ns-117.2 ns, respectively. It occupies an area of 80 µm×100 µm.

show abstract

A 1.99-ns 0.5-pJ Wide Frequency Range Level Shifter With Closed-Loop Negative Feedback

Cited by 6 publications

References 11 publications

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter

A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications

Contact Info

Product

Resources

About