A 1.8-V 3.1 mW successive approximation ADC in system-on-chip

Abstract

This paper describes a 10-bit 2.5 Msample/s successive approximation analog-to-digital converter (ADC) for SoC system. Based on conventional successive approximation ADC architecture a new and faster solution is used. The new solution consists of bootstrap switch, capacitors for sample-hold (S/H) circuit and DAC, using an offset cancellation method and there is no need for any active element. Together with an added bit and an offset compensation comparator the speed and accuracy is increased. The ADC exhibits higher 9 effective number of bits (ENOB) for sample rate to 2.5 Ms/s. The ADC consumes 3.1 mW from a 1.8 V supply and occupies about 0.25 mm 2 . The measured SNR is 56.05 dB.

Gain and offset correction methods for analog-to-digital converters

“…The proposed correction circuits can be used in any SC S/H [5][6][7] circuits based on Successive Approximation Register (SAR) ADC [8,9], which is chosen as the ADC type in this study due to its low power, moderate speed, and moderate accuracy.…”

An ultra low die area 8-b ADC and its generic calibration logic

“…On the contrary, applications like capacitance sensors and biosensor readout circuits, high fidelity sound processing systems etc., operate on input signals with frequencies of up to a few kHz but require ADCs of high accuracy in terms of static linearity and dynamic resolution [4][5][6][7][8][9]. A resolution higher than 8-bits is usually required in this case.…”