A 1.8-GHz CMOS Power Amplifier Using Stacked nMOS and pMOS Structures for High-Voltage Operation

A Three-Stage Inverter-Based Stacked Power Amplifier in 65 nm Complementary Metal Oxide Semiconductor Process

“…Except for the PA proposed by Son et al, 3) all of the proposed stacked PAs up to now were composed of only nMOS transistors. Although the PA by Son et al 3) uses both nMOS and pMOS transistors, it is not a real stacked PA since there are only two transistors that are in the stacked ladder of either nMOS or pMOS devices which their output power is combined via a transformer.…”

“…Except for the PA proposed by Son et al, 3) all of the proposed stacked PAs up to now were composed of only nMOS transistors. Although the PA by Son et al 3) uses both nMOS and pMOS transistors, it is not a real stacked PA since there are only two transistors that are in the stacked ladder of either nMOS or pMOS devices which their output power is combined via a transformer. The basic idea in this paper is replacing pMOS and nMOS transistors of a CMOS inverter with a stacked nMOS and a stacked pMOS devices respectively in which the stacked structure is expanded from the idea of the self-biased cascode.…”

“…With aggressive scaling down of the gate length in CMOS technology, unlike other RF blocks which benefit from this advancement, PA designers face more challenging task to get watt-level output power required in today's modern communication systems. 3) Main problems of CMOS PA design stem from intrinsic drawbacks of standard CMOS processes from RF perspectives. These problems are a low breakdown voltage and a high knee voltage [the voltage in transistor's current-voltage (I-V ) characteristics at which transition from linear to saturation occurs] of active devices; limiting allowable drain voltage swing; and increasingly highly doped, conductive substrates resulting in lossy onchip passive components leading to lossy and inefficient matching circuits.…”

“…These problems are a low breakdown voltage and a high knee voltage [the voltage in transistor's current-voltage (I-V ) characteristics at which transition from linear to saturation occurs] of active devices; limiting allowable drain voltage swing; and increasingly highly doped, conductive substrates resulting in lossy onchip passive components leading to lossy and inefficient matching circuits. 1,[3][4][5][6] Oxide breakdown and hot carrier effect are two problematic issues in PAs that originate from voltage stress on the CMOS transistor and get worse as the technology scales. 4) A simplified diagram of a PA is shown in Fig.…”