A 1.2V 20 dBm 60 GHz power amplifier with 32.4 dB Gain and 20 % Peak PAE in 65nm CMOS

Abstract

A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformerbased 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated output power (P SAT ) of 19.9 dBm and a 1-dB compressed output power (P -1dB ) of 17.2 dBm while achieving maximum power added efficiency (PAE max ) of 20 %. The small-signal gain is about 33 dB with a 3-dB bandwidth of 9 GHz. The circuit occupies an active area of 0.32 mm². To the author's knowledge, this amplifier presents the highest figure of merit (FoM ITRS) among 60 GHz PAs using silicon technology.

A 55-65 GHz Internal Differentially Matched Silicon Power Amplifier With Spirally Folded 1:2 Balun

“…to circuit performances. Compared to Wilkinson combiner PAs, transformer coupled ones [5], [14]- [17] save area of additional bias circuits by using center taps. This type of PA generally requires single-ended to differential signal conversion for the external I/O.…”

Compact high‐linearity, high‐efficiency complementary metal–oxide–semiconductor power amplifier with post‐distortion lineariser for wireless local area network and Wireless Gigabit Alliance applications

“…However, a CMOS transistor limits the output power of a PA owing to its low-Q passives, low break-down voltage and low transconductance. Proposed solutions include the use of cascode topology, multi-stage design and power combining technique to achieve high output power [7][8][9][10][11][12][13][14][15]. Enhancing the PAE of a PA extends the battery time of wireless portable equipment.…”

Power amplifier design for next generation WLAN

“…In [23], the PA achieves a P SAT of 11dBm CHAPTER 3 58 and a peak PAE of 14.6% at 64GHz, however, at 57GHz the P SAT is degraded to around 6.8dBm which is 4.2dB smaller, and the peak PAE is degraded to around 6% which is 8.6% smaller, as shown in Figure 3.15. The problem of large in-band degradation of performance can also be found in [24,26,27,29,30] as well.…”

“…It is often observed that some PAs for the 60GHz band have achieved good output power and efficiency in part of the bandwidth, but the output power and efficiency degrades a lot in the whole bandwidth of 57 to 66GHz [23][24][25][26][27][28][29][30].…”

“…This is a challenge, however, for CMOS PAs at mm-wave because of the low gain of transistors. As will be described in section 5.2, the power performance of a PA is not only related to the performance of the output stage but also highly related to that of the driver stages when the gain of transistors is [30],28nm SOI [27],40nm [26],65nm [24],90nm [23],90nm…”