A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOS

ADCs and DACs for Software‐Defined Radio

“…For example, using (6.1), the power consumption of a converter requiring 72 dB SNDR (i.e., 12 effective bits) over a bandwidth of 5 MHz can be estimated as follows: P = 65 fJ/conv. · 2 12 · 2 · 5 MHz = 2.66 mW (6.2) When comparing this estimation with real-world designs (e.g., [1,7]) one can see that it is an underestimation of real-world power. Nevertheless, this method is useful to give a generic idea of the feasibility of a certain set of specifications.…”

“…There are two methods of changing the signal bandwidth of the converter. The first one is simply to scale the sampling frequency [1,7,17] so that for the same OSR the signal bandwidth changes. This technique is very easy to implement, as it requires no additional circuitry.…”

“…When such circuits are operating at a lower frequency, they often have a large power overhead. Second, the OSR can be changed [7,17]. This has no consequences for an analog loop filter.…”

“…Introducing zeros can lead to a higher SNR [18]. In a reconfigurable ADC, the location of these zeros should be shifted depending on the signal bandwidth wanted [7,17].…”

“…When converting signals from other standards, the capacitors' size and hence the OTA current required can be decreased [7]. Figure 6.8 shows the operation of an m-stage, n-bit per stage pipelined converter.…”