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The performances of continuous time delta sigma converters are severely affected by clock jitter and no generic technique to predict the corresponding degradations is nowadays available. This paper presents a new analytical approach to quantify the power spectral density of jitter errors. This generic computational method can be applied to all kind of continuous time delta sigma converters. Furthermore, clock imperfections are described by means of phase noise spectrum, consequently all possible type of jitters can be taken into account. This paper also describes the temporal non ideal clock models that have been created to simulate the impact of jitter on delta sigma converters and validate the theoretical results.

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This study suggests several analogue bandwidth mismatch compensation techniques for time-interleaved analogue-to-digital converters. All the techniques adjust the equivalent on-resistance of the track and hold (T/H) under calibration. Simulations of a two-channel time interleaved T/H running at f s = 4 GHz shows the effectiveness of the proposed compensations.