A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS

Damodaran, R.; Anderson, Timothy R.; Agarwala, S.; Venkatasubramanian, R.; Gill, Michael; Gopalakrishnan, Dhileep; Hill, Anthony; Chachad, A.; Balasubramanian, Dheera; Bhoria, Naveen; Tran, J.; Bui, Duc; Rahman, Mujibur; Moharil, Shriram; Pierson, Matthew; Mullinnix, S.; Ong, Hung; Thompson, David W.; Gurram, Krishna; Olorode, Oluleye; Mahmood, Nuruddin; Flores, J.; Rajagopal, Arjun; Narnur, Soujanya; Wu, Daniel; Hales, Alan; Peavy, Kyle; Sussman, Robert W.

doi:10.1109/vlsid.2012.85

Cited by 14 publications

(8 citation statements)

References 6 publications

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“…The RTL VCD based power integrity analysis presented in this paper is evaluated in the context of this multicore SoC. Texas Instruments C66x DSP [14] is a high performance DSP core that supports integrated fixed-point and floatingpoint operations, leveraging 8-way VLIW to issue up to 8 new operations every cycle. The DSP core block diagram is shown in Figure 5.…”

Section: Ti Keystone Multicore Soc and C66x Dspmentioning

confidence: 99%

Perils of power prediction in early power-integrity analysis

Arun

Stelmach

Venkatasubramanian

et al. 2014

2014 IEEE Dallas Circuits and Systems Conference (DCAS)

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Early power integrity and peak power analyses for multi-million gate system on chip (SoC) in advanced technology nodes pose significant methodology definition and implementation challenges. Typically in a SoC, processors and other high performance IPs are dominant contributors to peak power and power integrity issues. To get an early look ahead of potential power integrity issues and to estimate peak di/dt issues in the SoC, it is always desired to analyze potential issues early and address before a silicon failure. This paper presents an overview of implementation challenges faced in RTL based power for predictive power analysis and analyzing peak di/dt issues ahead of time in the context of TI C66x DSP core based multicore SoC.

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Section: Ti Keystone Multicore Soc and C66x Dspmentioning

confidence: 99%

Perils of power prediction in early power-integrity analysis

Arun

Stelmach

Venkatasubramanian

et al. 2014

2014 IEEE Dallas Circuits and Systems Conference (DCAS)

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“…TMS320C66x DSP [1] is the high performance DSP core from Texas Instruments and has integrated fixed-and floating-point operation support, leveraging 8-way VLIW to issue up to 8 new operations every cycle, with SIMD operations for fixed point and fully-pipelined instructions, with support for up to 32, 8-bit or 16-bit multiplies per cycle, up to eight, 32-bit multiplies per cycle. Floating point support on the core allows up to eight single-precision multiplies per cycle, or up to two doubleprecision multiplies per cycle.…”

Section: C66x Dsp Corementioning

confidence: 99%

“…The C66x DSP [1] is one of the high performance DSP's from Texas Instruments and is extensively used in many heterogeneous multicore Soc's (Multicore ARM + DSP Soc's). Typically, each processor core is operated in a separate powerdomain.…”

Section: Introductionmentioning

confidence: 99%

State Retention Validation of C66X DSP Core

Venkatasubramanian

Olorode

Arun

2013

2013 14th International Workshop on Microprocessor Test and Verification

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Low power design has become an important design requirement in any deep-submicron CMOS design development. State retention using retention flip flops is one of the low power techniques that offer the ability to save and restore the state of the design during a period of inactivity (IDLE or STANDBY mode). Since processor cores typically have a well-defined period of operation and inactivity, the state retention scheme is well suited for processor designs. This paper provides an overview of the various state retention implementation choices for processor cores and explains the state retention validation methodology for the different implementations. The state retention and validation methodology deployed for the TI C66x Core is explained in detail.

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“…Most of their processors are available in multiple configurations, which means that at least the number of cores can be selected. TI DSPs very much rely on VLIW architectures with shared memory and cache hierarchies [58,59]. The processors may come equipped with special hardware to accelerate certain algorithms, e.g.…”

Section: Texas Instruments Dspsmentioning

confidence: 99%

“…The c66x power estimate of 1180mW from [59] is used and the performance estimation is based on the stated number of clock cycles per pixel according to [145]. In practice there will be additional overheads.…”

Section: Non-power-of-2 Transformsmentioning

confidence: 99%

Design of Energy-Efficient High-Performance ASIP-DSP Platforms

Karlsson¹

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Cover imageChip layout of an ePUMA system with 8 compute clusters, each with a local controller, 8 compute cores and 1536kB of local compute data memory. The complete chip contains 73 processor cores and occupies 45mm 2 in 28nm FDSOI technology.(Parts of this thesis are reprinted with permission from the IEEE.)Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2016 AbstractIn the last ten years, limited clock frequency scaling and increasing power density has shifted IC design focus towards parallelism, heterogeneity and energy efficiency. Improving energy efficiency is by no means simple and it calls for a reevaluation of old design choices in processor architecture, and perhaps more importantly, development of new programming methodologies that exploit the features of modern architectures.This thesis discusses the design of energy-efficient digital signal processors with application-specific instructions sets, so-called ASIP-DSPs, and their programming tools. Target applications for such processors include, but are not limited to, communications, multimedia, image processing, intelligent vision and radar. These applications are often implemented by a limited set of kernel algorithms, whose performance and efficiency are critical to the application's success. At the same time, the extreme non-recurring engineering cost of system-on-chip designs means that product life-time must be kept as long as possible. Neither general-purpose processors nor non-programmable ASICs can meet both the flexibility and efficiency requirements, and ASIPs may instead be the best trade-off between all the conflicting goals.Traditional superscalar-and VLIW processor design focus has been to improve the throughput of fine-grained instructions, which results in high flexibility, but also high energy consumption. SIMD architectures, on the other hand, are often restricted by inefficient data access. The result is architectures which spend more energy and/or time on supporting operations rather than actual computing. In addition to the hardware design, this thesis also discusses parallel programming flow for distributed memory architectures and ePUMA application implementation. A DSP kernel programming language and its compiler is presented. This effectively demonstrates how kernels written in a high-level language can be translated into HOF instructions for very high processing efficiency. Populärvetenskaplig sammanfattning PrefaceThis thesis includes material from the following first-author publications:• Andréas Karlsson, Joar Sohl and Dake Liu.Energy-efficient sorting with the distributed memory architecture ePUMA. In Proceedings of the International Symposium on Parallel and Dis-tributed Processing with Applications (ISPA), 2015.• Andréas Karlsson, Joar Sohl and Dake Liu. Cost-efficient Mapping of 3-and 5-point DFTs toGeneral Baseband Processors. In Proceedings of the International Conference on Digital SignalProcessing (DSP), 2015.• Andréas Karlsson, Joar Sohl and Dake Liu. Software-based QPP Interleaving forBaseband DS...

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A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS

Cited by 14 publications

References 6 publications

Perils of power prediction in early power-integrity analysis

Perils of power prediction in early power-integrity analysis

State Retention Validation of C66X DSP Core

Design of Energy-Efficient High-Performance ASIP-DSP Platforms

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