A 1.2 – 6.4 GHz clock generator with a low-power DCO and programmable multiplier in 40-nm CMOS

Abstract

This paper presents a clock generator for a MIPI M-PHY serial link transmitter, which includes an ADPLL, a digitally controlled oscillator (DCO), a programmable multiplier, and the actual serial driver. The paper focuses on the design of a DCO and how to enhance the frequency resolution to diminish the quantization noise introduced by the frequency discretization. A s a r e s u l t , a 1 7 -k H z D C O f r e q u e n c y t u n i n g r e s o l u t i o n i s demonstrated. Furthermore, implementation details of a lowpower programmable 1-to-2-or-4 frequency multiplier are elaborated. The design has been implemented in a 40-nm CMOS process. The measurement results verify that the circuit provides the MIPI clock data rates from 1.248 GHz to 5.83 GHz. The DCO and multiplier unit dissipates a maximum of 3.9 mW from a 1.1 V supply and covers a small die area of 0.012 mm 2 .

Delay Elements Suitable for CMOS Ring Oscillators

“…The DE which is based on a balanced current-starved inverter structure, M n1+ /M p2+ and M n1-/M p2-, is shown in Fig. 5 [6]. The frequency tuning is achieved using the current starving technique, which has been implemented using the control current I CTRL .…”

“…Including the proposed DE into a RO we achieve an oscillation frequency which is actually proportional to V CTRL . The frequency tuning is achieved without using current starving as in [6]. The current through M p2+ -M p2-which charges the parasitic capacitance of the output nodes follows the changes of the V CTRL .…”

A 3GHz VCO suitable for MIPI M-PHY serial interface

“…The performance of the proposed VCO is compared with two state-of-the-art implementations [19], [20]. The main target specification for both designs was the phase noise to be around -94 dBc/Hz.…”

Multi-data rate receiver for high-speed serial interfaces

“…Owing to the fact that the design of the RX-PLL is outside the objectives of this thesis, an explicit value for the RJrms,rxclk is not available and so a realistic approximation of it must be realized. According to several published works in the literature [139], [140], [141] , the design of a PLL switable for HSSIs RX applications operating near the required frequency (i.e 3GHz), of even lower than 0.003UI or 0.5ps rms RJrms is feasible. Although in order to ease the requirments for the RX-PLL block, we assummed a RJrmx,rxclk value equal to 1ps or 0.006UI which corresponds to a tmargin equal to 0.235UI.…”

“…Both simulation results presented in Figure 6.42 and Figure 6.43 are refered in operation with 6-Bit CDR loop filter. Alternatively, a wide range programmable frequency multiplier combined with a VCO at the lowest frequency band can be employed making the overall design more flexible [141]. The frequency multiplier actually multiplies the low frequency clock of an oscillator with a programmable multiplication factor, offering the required high frequency clocks to the system.…”