Figure 1: EBL buffer schematic and operation II. ENHANCED BOOST LOGIC T(ns) Evaluation Phase 0.4 pc pc bpc equal-clock -speed static CMOS implementation. At its resonant frequency of 466MHz, the FIR chip dissipates 39.1mW, yielding a figure of merit equal to 93.6nW/MHz/Tap/lnBit/CoeffBit, a 29% improvement over previously-reported high-performance FIRs running above 500MHz [6,7] . Fabricated in a O.131lm CMOS process, the chip includes a 3nH on-chip inductor and integrated clock generator with frequency scaling capability. Correct operation has been validated across the 365-600MHz range. When operating at its resonant frequency of 466MHz, the chip recovers 45% of the energy supplied to it by the two charge-recovery phases. Figure I shows a cascade of EBL buffers and their operation . Similar to Boost Logic [5], EBL operates in two stages. The dual-rail evaluation stage is implemented with a pull-up network (PUN) and a pull-down network (PDN) that use only NMOS devices and are powered by a single near-threshold DC supply (VCC).The NMOS in the PDN achieve gate overdrive ervnn.v., The NMOS in the PUN achieve greater gate overdrive compared to a PMOS implementation, since the input can swing to full VDD at 1.2V, while the evaluation supply is near-threshold. The boost stage consists of a cross-coupled inverter with the source of the PMOS connected to a charge-recovering power clock phase pc .