A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Kuroda, Tadahiro; Fujita, Takeshi; Mita, Shiro; Nagamatsu, T.; Yoshioka, Shinichi; Suzuki, Kôjiro; Sano, Fumihiko; Norishima, M.; Murota, Masayuki; Kako, M.; Kinugawa, M.; Kakumu, M.; Sakurai, Takayasu

doi:10.1109/jssc.1996.542322

Cited by 362 publications

(141 citation statements)

References 7 publications

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“…Table II lists features of the proposed processor and other DCT implementations selected from among those which fulfill the specifications of the standard [2]. The parallel-pipeline architecture and arithmetic units operating at half the frequency gives an input data rate of 300MHz, far higher than that of the fastest processor listed in this table [3] [7]. This speed does not imply any additional cost in terms of the number of gates since it offers an efficient hardware implementation.…”

Section: Implementation and Comparisonsmentioning

confidence: 99%

“…Thus, the DCT has been applied for most of recent picture international standards as JPEG, MPEG, H.261 and H.263, as well as in high-definition television (HDTV) systems. The computation complexity requirements in many real-time applications often lead to the use of efficient dedicated hardware (ASIC's) operating at high speed with an acceptable cost in area [3]- [7]. This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with a high input data rate and a cost-effective hardware.…”

Section: Introductionmentioning

confidence: 99%

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High throughput 2D DCT/IDCT processor for video coding

Ruiz

Michell

Burón

2005

IEEE International Conference on Image Processing 2005

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This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the processing elements and arithmetic units to work in parallel at half the frequency of the data input rate. A fully pipelined row-column decomposition method based on two 1-D DCTs and a transpose buffer based on D-type flip-flops are used. The processor has been implemented in a 0.35-µm CMOS process with a core area of 3mm 2 and 11.7k gates. It meets the requirements of IEEE Std. . The data input rate frequency is 300MHz with a latency of 172 cycles for 2-D DCT and 178 cycles for 2-D IDCT. The proposed design is compact and suitable for HDTV applications.

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Section: Implementation and Comparisonsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High throughput 2D DCT/IDCT processor for video coding

Ruiz

Michell

Burón

2005

IEEE International Conference on Image Processing 2005

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“…In spite of this, there are major drawbacks with the use of MTCMOS technique. [3] these drawbacks are non retention of data by memories and flip-flop. The other one is Variable-ThresholdVoltage CMOS (VTCMOS) [4].…”

Section: Introductionmentioning

confidence: 99%

Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology

Pandey¹,

Akashe²

2014

IJCA

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Reduction of power dissipation is one of the most important challenges in VLSI circuit design. Due to scaling, sub threshold leakage current plays a dominant role in total power dissipation. This paper illustrates application of power saving SVL technique on 2:1 NAND MUX architecture. This application offers significant reduction in leakage power and leakage current viz-a-viz previous techniques. Self controllable Voltage Level Circuit (SVL) technique drastically reduces stand by leakage power and leakage current of CMOS logic circuits. This technique compare the optimization of leakage current and leakage power using two different design of 2:1 MUX. First is conventional MUX and other one is NAND based 2:1 MUX. The performance of this designed circuit is realized on a standard 45nm technology by using 0.7v supply voltage. It is easily concluded that this 2:1 nand based MUX achieves 651.9 Pw leakage power (Pst) and leakage current 1.020nA in standby mode, Where as conventional MUX achieved 2.04nA leakage current and 0.5nW leakage power.

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“…However, when the values of supply voltage V DD and threshold voltage V th of MOSFETs come close, the variation of threshold voltage has a significant impact on circuit performance. This is because the saturation current of a MOSFET depends on both supply voltage V DD and threshold voltage V th , and the variation of the current is proportional to the expression of α/(V DD − V th ), where α is a carrier mobility degradation factor [2], [3]. Both low supply voltage operation and the use of high V th MOSFET therefore tend to increase variation in circuit performance.…”

Section: Introductionmentioning

confidence: 99%

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

Tsugita

Ueno

Hirose³

et al. 2010

IEICE Trans. Electron.

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SUMMARYAn on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-μm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.

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A 0.9-V, 150-MHz, 10-mW, 4 mm/sup 2/, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Cited by 362 publications

References 7 publications

High throughput 2D DCT/IDCT processor for video coding

High throughput 2D DCT/IDCT processor for video coding

Design Techniques for Self Voltage Controllable Circuit on 2:1 Multiplexer using 45nm Technology

An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs

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