A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration

Liempd, Barend van; Borremans, Jonathan; Martens, Ewout; Cha, Sungwoo; Suys, Hans; Verbruggen, Bob; Craninckx, Jan

doi:10.1109/jssc.2014.2321148

Cited by 80 publications

(36 citation statements)

References 21 publications

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“…A harmonic rejection mixer scheme, which was first proposed in [2] for a transmitter design, has been widely adopted in modern wideband RF receiver designs [3][4][5][6][7][8][9][10][11] to alleviate this problem. The basic idea is to construct an equivalent LO signal that is free of 3rd and 5th order harmonics, such that the 3rd and 5th order harmonic interferer would not be down-converted by the mixer, therefore being completely rejected.…”

Section: Harmonic Rejection Schemementioning

confidence: 99%

“…In addition to relying on the intrinsic matching of CMOS process, calibration methods [7,8] have also been proposed to increase the HRR. These methods rely on a common technique in which gain mismatch cancels phase mismatch.…”

Section: Previous Work On Achieving High Hrrmentioning

confidence: 99%

“…However, different phase and gain setting are needed to optimize HRR 3 and HRR 5 , respectively, resulting in the optimization of either HRR 3 or HRR 5 , not both. In [7,8] the authors calibrate the gain mismatch of the HR mixers and achieve a HRR 3 of approximately 70 dB. However, a degradation of HRR 5 after HRR 3 calibration is reported in [7].…”

Section: Previous Work On Achieving High Hrrmentioning

confidence: 99%

“…This calibration was performed on the clocking signal of the differential latches. Inverters INV [5][6][7][8][9][10][11][12] , which buffer the LO outputs, were also designed to be tunable with the ESES method for differential phase mismatch calibration for even order HR.…”

Section: Multi-phase Lo Generator With Eses-based Tunable Phasementioning

confidence: 99%

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A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

2016

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Section: Harmonic Rejection Schemementioning

confidence: 99%

Section: Previous Work On Achieving High Hrrmentioning

confidence: 99%

Section: Previous Work On Achieving High Hrrmentioning

confidence: 99%

Section: Multi-phase Lo Generator With Eses-based Tunable Phasementioning

confidence: 99%

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A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

2016

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“…To achieve high resilience to out-of-band interference, a high linearity transconductor is wanted. Many recent receiver front-ends [11], [13]- [16] use a CMOS inverter as a transconductor due to its high linearity and relatively good normalized signal-to-noise ratio [17]. However, this linearity is achieved by "complementary derivative superposition" [18], which relies on cancellation of PMOS and NMOS transistors' distortion terms.…”

mentioning

confidence: 99%

RF Transconductor Linearization Robust to Process, Voltage and Temperature Variations

Subramaniyan

Klumperink

Srinivasan

et al. 2015

IEEE J. Solid-State Circuits

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Software-defined radio receivers increasingly exploit linear RF V-I conversion, instead of RF voltage gain, to improve interference robustness. Unfortunately, the linearity of CMOS inverters, which are often used to implement V-I conversion, is highly sensitive to Process, Voltage and Temperature variations. This paper proposes a more robust technique based on resistive degeneration. To mitigate third-order IM3 distortion induced by the quadratic MOSFET I-V characteristic, a new linearization technique is proposed which exploits a floating battery by-pass circuit and replica biasing to improve IIP3 in a robust way. This paper explains the concept and analyzes linearity improvement. To demonstrate operation, an LNTA with current domain mixer is implemented in a 45 nm CMOS process. Compared to a conventional inverter based LNTA with the same transconductance, it improves IIP3 from 2 dBm to a robust P IIP3 of 8 dBm at the cost of 67% increase in power consumption.Index Terms-CMOS, cognitive radio receiver, figure-of-merit, IIP3, linearity, linearization, multi-band receiver, negative feedback, process voltage temperature (PVT) variations, receiver, reconfigurable receiver, robust circuit design, SAW-less receiver, software-defined receiver, software-defined radio, transconductor, wideband receiver.

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A switch‐controlled multimode narrowband receiver RF front‐end

Wang

Zhu

et al. 2019

Int J Communication

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Summary This work illustrates a flexible and convenient method to build a multimode narrowband receiver RF front‐end by means of controlled switches, switched capacitors, and switched inductors. The front‐end comprises a dual‐gain‐mode narrowband low‐noise amplifier (LNA) and a dual‐linearity‐mode mixer. A four‐mode receiver RF front‐end constructed with the dual‐gain‐mode LNA and the dual‐linearity‐mode mixer operating in frequency band range from 1800 to 2050 MHz was demonstrated with an IBM 90‐nm CMOS process. The front‐end achieves a 1/1.6 dB noise figure, 30/20 dB power gain, and 16/−10 dBm third‐order input intercept point while draws a 5.9/3.6 mA current from a 1.8‐V supply voltage at the low noise mode and high linearity mode, respectively. The proposed technique can be employed to build an intelligent mobile system.

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A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration

Cited by 80 publications

References 21 publications

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

RF Transconductor Linearization Robust to Process, Voltage and Temperature Variations

A switch‐controlled multimode narrowband receiver RF front‐end

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