2018 IEEE International Solid - State Circuits Conference - (ISSCC) 2018
DOI: 10.1109/isscc.2018.8310376
|View full text |Cite
|
Sign up to set email alerts
|

A 0.8V 0.8mm2 bluetooth 5/BLE digital-intensive transceiver with a 2.3mW phase-tracking RX utilizing a hybrid loop filter for interference resilience in 40nm CMOS

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1
1
1

Citation Types

0
49
0

Year Published

2018
2018
2022
2022

Publication Types

Select...
4
3

Relationship

0
7

Authors

Journals

citations
Cited by 32 publications
(55 citation statements)
references
References 6 publications
0
49
0
Order By: Relevance
“…Reported works suggest that ULV and ULP currently stand for supply voltages under 1.0 V and RF receiver power consumption under 3.0 mW [7][8][9].…”
Section: Motivationmentioning
confidence: 99%
See 3 more Smart Citations
“…Reported works suggest that ULV and ULP currently stand for supply voltages under 1.0 V and RF receiver power consumption under 3.0 mW [7][8][9].…”
Section: Motivationmentioning
confidence: 99%
“…where This work contemplate the adoption of a Low-IF receiver, taking into account the benefit of avoiding DC offset and flicker noise [7,10,32] influence in the DC spectrum [8,9,11,[33][34][35][36].…”
Section: Wireless Receiver Architecture For Blementioning
confidence: 99%
See 2 more Smart Citations
“…A smaller power dissipation, at the transmitter part, is obtained by using all-digital circuits (KUO et al, 2017;LIU et al, 2015) or operating at the ultra-low voltage range (ULV) (YIN et al, 2018). On the other hand, at the receiver (RX) part, the smaller power dissipation is obtained using modern Low-IF and Zero-IF architectures, operating with low voltage supply (ZHANG; MIYAHARA; OTIS, 2013; YI BRYANT;SJOLAND, 2014;SELVAKUMAR;LISCIDINI, 2015;DING et al, 2018;KUO et al, 2018), or by reducing the number of RF active blocks (MASUCH; DELGADO-RESTITUTO, 2013a; BRYANT; SJOLAND, 2014). The digital-intensive circuits transceivers should be implemented in advanced CMOS process (≤ 40 nm) in order to obtain faster switches and lower parasitic capacitances (KUO et al, 2018).…”
Section: Introductionmentioning
confidence: 99%