A 0.7V 17fJ/Step-FOMW 178.1dB-FOMSNDR 10kHz-BW 560mVPP True-ExG Biopotential Acquisition System with Parasitic-Insensitive 421MΩ Input Impedance in 0.18μm CMOS

Lee, Se-Hwan; Choi, Yongjun; Kim, Geunha; Baik, Seungyeob; Seol, Taeryoung; Jang, Homin; Lee, Doyoung; Je, Minkyu; Choi, Ji‐Woong; George, Arup K.; Lee, Junghyup

doi:10.1109/isscc42614.2022.9731114

Cited by 6 publications

(2 citation statements)

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“…However, due to its complex signal chain, recording chips that employ this architecture often require significant power consumption and area. The second architecture of recording chips omits the low noise amplifiers and directly quantizes neural signals using a low noise ADC [20,21,22,23,24,25,26,27,28,29,30]. Due to its simplified signal processing chain, this architecture can often achieve a low single-channel area [23,24,25,26,27], or a large input range with low power consumption [28,29,30], making it highly promising for future research.…”

Section: Introductionmentioning

confidence: 99%

“…The second architecture of recording chips omits the low noise amplifiers and directly quantizes neural signals using a low noise ADC [20,21,22,23,24,25,26,27,28,29,30]. Due to its simplified signal processing chain, this architecture can often achieve a low single-channel area [23,24,25,26,27], or a large input range with low power consumption [28,29,30], making it highly promising for future research. [25] proposed a DC coupled input, two-step quantization incremental ΔΣ ADC that exhibits superior performance.…”

Section: Introductionmentioning

confidence: 99%

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A 16-µW 10-kHz BW incremental ΔΣ ADC with automatic EDO canceling for implantable neural recording

Zhang,

Liu,

Yang

et al. 2024

IEICE Electron. Express

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This paper presents a DC-coupled, incremental ΔΣ analog-to-digital converter (ADC) based on two-step quantization for high-density implantable neural signal recording. To address the problem of electrode DC offset (EDO), a compensation circuit is proposed in this paper which can automatically cancel the EDO. Fabricated in a 180-nm CMOS process, the prototype ADC achieves a high input impedance, 20-mVpp linear input range, 60.3-dB signal-to-noise and distortion ratio (SNDR). Its core circuit has a power consumption of 16 𝜇W and an area of 0.0165𝑚𝑚 2 .The referedto-input (RTI) noise is 6 𝜇Vrms (1-10kHz) and it can cancel the EDO up to ±90𝑚𝑉 .

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