A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

Choi, Sung‐Yool; Sohn, Kiwon; Lee, Min-Wuk; Kim, Sun‐Young; Choi, Hyemi; Kim, Dong-Hyun; Cho, Uk-Rae; Byun, Hyun-Geun; Shin, Yun-Seung; Yoo, Hoi‐Jun

doi:10.1109/jssc.2004.837979

Cited by 59 publications

(7 citation statements)

References 9 publications

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“…Finally, the proposed 9T-2MTJcell-based nonvolatile TCAM achieved search energy of 0.73 fJ/bit/search which is comparable to recent CMOSbased TCAM with realizing smaller cell transistor counts, lower standby power, and higher search speed. 26)…”

Section: Evaluationsmentioning

confidence: 99%

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

Matsunaga

Katsumata

Natsui

et al. 2012

Jpn. J. Appl. Phys.

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Towards a low search-energy nonvolatile ternary content-addressable memory (TCAM), we propose a novel nine-transistor/two-magnetic-tunnel-junction (9T–2MTJ) nonvolatile TCAM cell circuit with a high-speed accessibility. Since critical path for switching in the TCAM cell circuit is only a single metal-oxide-semiconductor (MOS) transistor, switching delay of the TCAM word circuit is minimized. As a result, the worst-case switching delay of 0.22 ns is achieved in a 144-bit word circuit under a 90 nm complementary MOS (CMOS)/MTJ technology, which is about 2.6 times faster than that of a conventional CMOS-based TCAM. In order to minimize the active power dissipation in the proposed TCAM, a multi-level segmented match-line scheme that maximally brings inessential cells to standby state is also applied to the 9T–2MTJ-cell-based word circuit. Finally, low search-energy of 0.73 fJ/bit/search is achieved in a 144-bit × 256-word nonvolatile TCAM together with eliminating standby power using nonvolatility.

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Section: Evaluationsmentioning

confidence: 99%

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

Matsunaga

Katsumata

Natsui

et al. 2012

Jpn. J. Appl. Phys.

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“…However, this architecture might lead to an increase in power consumption, due to the contemporary and continuous comparison activity in every device cell [3]. For this reason, different hardware solutions, based on particular single-bit cells [3][4][5][9][10][11] or various power saving algorithms [11][12][13], have been explored in the past.…”

Section: Introductionmentioning

confidence: 99%

“…The novelty of this work, compared to the state-of-the-art, is the presentation of a Content Addressable Memory developed with a full-custom design approach in the 28 nm CMOS-Bulk node (CAM-28CB). The highly downscaled technology node offers a speed increase, without a power consumption increase (with the standard digital design flow, a device speed increase and a size reduction, up to a factor of 3, result, compared to the CMOS 65 nm node [3,9]). Moreover, the main aim of this work is to produce aggressive power reduction achieved with a full-custom design, both in the schematic and the layout phase.…”

Section: Introductionmentioning

confidence: 99%

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A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments

Fary

Basçhirotto

2020

JLPEA

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This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), in order to achieve very low-power and high-speed performances. The proposed architecture does not require an internal clock or pre-charge phase, which usually increase the power request and slow down data searches. On the other hand, the dedicated solutions are exploited in order to minimize parasitic layout-induced capacitances in the single-bit cell, further reducing the power consumption. The prototype device, named CAM-28CB, is integrated in the deeply downscaled 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) Bulk (28CB) technology. In this way, the high transistor transition frequency and the intrinsic lower parasitic capacitances allow the system speed to be improved. Furthermore, the high radiation hardness of this technology node (up to 1Grad TID), together with the CAM-28CB high-speed and low-power performances, makes this device suitable for High-Energy Physics experiments, such as ATLAS (A Toroidal LHC ApparatuS) at Large Hadron Collider (LHC). The prototype operates at a frequency of up to 100 MHz and consumes 46.86 µW. The total area occupancy is 1702 µm2 for 1.152 kb memory bit cells. The device operates with a single supply voltage of 1 V and achieves 0.41 fJ/bit/search Figure-of-Merit.

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“…For example, the SL power consumption in Refs. [24][25][26] amounted to about 46%, 71%, and 82% of the total power, respectively.…”

Section: Introductionmentioning

confidence: 99%

A cascaded charge-sharing technique for an EDP-efficient match-line design in CAMs

Zhang¹,

Ye²,

Liu³

et al. 2009

J. Semicond.

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A novel cascaded charge-sharing technique is presented in content-addressable memories (CAMs), which not only effectively reduces the match-line (ML) power by using a pre-select circuit, but also realizes a high search speed. Pre-layout simulation results show a 75.9% energy-delay-product (EDP) reduction of the MLs over the traditional precharge-high ML scheme and 41.3% over the segmented ML method. Based on this technique, a test-chip of 64-word × 144-bit ternary CAM (TCAM) is implemented using a 0.18-µm 1.8-V CMOS process, achieving an 1.0 ns search delay and 4.81 fJ/bit/search for the MLs.

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A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

Cited by 59 publications

References 9 publications

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

Design of a Nine-Transistor/Two-Magnetic-Tunnel-Junction-Cell-Based Low-Energy Nonvolatile Ternary Content-Addressable Memory

A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments

A cascaded charge-sharing technique for an EDP-efficient match-line design in CAMs

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