A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD_min VLSIs

Chen, Y.H.; Chan, Wei-Min; Chou, Shau-Yu; Liao, Haijun; Pan, Hsien-Yu; Wu, J. J.; Lee, C.H.; Yang, Shuting; Liu, Y.C.; Yamauchi, Hiroyuki

doi:10.1109/vlsic.2008.4586010

Cited by 27 publications

(18 citation statements)

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“…The second method is to collapse V DD , which weakens the pull-up transistors [4,9,10]. The third and fourth methods involve strengthening the pass-gate transistors by either boosting the WL V DD or reducing the BL V SS [4][5][6][7][8]11,13]. These methods strengthen the passgate by increasing its V GS .…”

Section: Write Assist Methodsmentioning

confidence: 99%

“…The first is to improve the stability of the cross-coupled inverters during the read by either raising the bitcell V DD or reducing its V SS [4,5,[7][8][9][10]. While raising bitcell V DD has been shown by [2] to result in larger gains in RSNM, the advantage of reducing the bitcell V SS is that it significantly reduces read delay due to the body effect strengthening both the pull-down and pass-gate transistors [2].…”

Section: Read Assist Methodsmentioning

confidence: 99%

“…This paper provides a comparison of four different bitcell topologies using read and write V MIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4][5][6][7][8][9][10][11][12][13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV.…”

Section: Introductionmentioning

confidence: 99%

“…The downside to this strategy is that adding more transistors to the bitcell increases the total area of the array. The second strategy is to use various assist methods [4][5][6][7][8][9][10][11][12][13] to make the cell easier to read and write. This method also results in a smaller area overhead and may require multiple voltage sources.…”

Section: Introductionmentioning

confidence: 99%

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Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Boley

Wang

Calhoun

2012

JLPEA

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Abstract:The need for ultra low power circuits has forced circuit designers to scale voltage supplies into the sub-threshold region where energy per operation is minimized [1]. The problem with this is that the traditional 6T SRAM bitcell, used for data storage, becomes unreliable at voltages below about 700 mV due to process variations and decreased device drive strength [2]. In order to achieve reliable operation, new bitcell topologies and assist methods have been proposed. This paper provides a comparison of four different bitcell topologies using read and write V MIN as the metrics for evaluation. In addition, read and write assist methods were tested using the periphery voltage scaling techniques discussed in [4][5][6][7][8][9][10][11][12][13]. Measurements taken from a 180 nm test chip show read functionality (without assist methods) down to 500 mV and write functionality down to 600 mV. Using assist methods can reduce both read and write V MIN by 100 mV over the unassisted test case.

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Section: Write Assist Methodsmentioning

confidence: 99%

Section: Read Assist Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Boley

Wang

Calhoun

2012

JLPEA

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“…So, different topologies of SRAM cell have been implemented at various technologies to improve the data stability and leakage power consumption. Various topologies of SRAM cell has been introduced, 7T SRAM cell in which a read static noise margin is achieved by cutting off a pull down path during read operation but has limited write capability due to single end write operations [6], [7].8T SRAM cell which is one of the popular topology which increases the stability but has its own limitation. In this paper the limitation of 8T has been removed and alternative topologies have been discussed to increase the stability.…”

Section: Conventional Sram Cellmentioning

confidence: 99%

Characterization of 9T SRAM Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia Applications

Singh¹,

Birla²,

Pattanaik³

2011

IJET

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Abstract-In the past decades CMOS IC technologies have been constantly scaled down and at present they aggressively entered in the nanometer regime. Amongst the wide-ranging variety of circuit applications, integrated memories especially the SRAM cell layout has been significantly reduced. As it is very well know the reduction of size of CMOS involves an increase in physical parameters variation, this is a factor which has a direct impact on SRAM cell stability. Polysilicon and diffusion critical dimensions (CD) together with implant variations are the main causes of mismatch in SRAM cells. SRAM memory cells have always been designed to occupy the minimum amount of silicon area consistent with the performance and reliability required. Today's system on Chip (SoC) trends result in a major percentage of the total die area being dedicated to memory blocks, consequently making SRAM parameter variations dominate the overall circuit parameter characteristics, including leakage, process variation effects, etc. The reliability is usually measured by static noise margin, SNM [1], and write trip point simulations and measurements. In this paper we have analyzed the stability of the 9T SRAM cell at SS, FF, TT, FS, SF corners. The simulations have been done at 45nm technology.Index Terms-SOCs, Embedded SRAM, Scaling, Deep submicron level. I. INTRODUCTIONSubthreshold leakage and gate current are not the only issues that have to be deal at a functional level, but at the same time the power management issues of chips for high-performance circuits such as microprocessors, digital signal processors, and graphics processing units are also necessary. Power management is also a challenge in mobile/multimedia applications. Device variations causing device mismatch for several reasons make the memory more sensitive in terms of stability. For stable read and write, the memory cells must be able to keep the stored state when accessed for reading but quickly change state when accessed for writing. These conflicting needs are even more difficult to achieve with the process variations of sub-100 nm processes.As the lithography shrinks, the device variations are becoming an ever increasing concern. With the sub-100 nm processes, statistical variations need to be included in the SRAM cell and SRAM block analysis to attain circuit designs with sufficient yield and performance within a defined limited area and power budget. On the contrary, the transistor and SRAM bit cell size reduction driven by the technology scaling has also made it even more challenging to maintain a sufficient cell stability margin while keeping the same scaling pace of access time and cell size as the mismatching of threshold voltage (Vt) between cross-coupled MOSFET pairs becomes larger and larger [1], [2], [3]. To maintain sufficient margins for read and write stability and read cell current has become challenging as Vdd has to be scaled down in order not only to meet the requirements for device scaling and power savings but also to keep the logic operating voltage c...

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Embedded SRAM Design in Nanometer-Scale Technologies

Yamauchi

2009

Integrated Circuits and Systems

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A 0.6V 45nm adaptive dual-rail SRAM compiler circuit design for lower VDD_min VLSIs

Cited by 27 publications

References 0 publications

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM VMIN

Characterization of 9T SRAM Cell at Various Process Corners at Deep Sub-micron Technology for Multimedia Applications

Embedded SRAM Design in Nanometer-Scale Technologies

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