A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface

Jeong, Yong-Un; Park, Hyunkyu; Hyun, Chang‐Ho; Chae, Joo-Hyung; Jeong, Shin-Hyun; Kim, Suhwan

doi:10.1109/jssc.2020.3042240

Cited by 24 publications

(13 citation statements)

References 22 publications

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“…signal linearity, have been recently reported [5,[11][12][13]. However, in previous designs [5,11,12], the signal level distortion cannot be alleviated while matching the channel impedance, or the output impedance is calibrated based on only one output level; thus, impedance mismatch can occur at other signal levels.…”

Section: Design Considerationsmentioning

confidence: 99%

“…The conventional ZQ calibration is carried out based on one level [5]; thus, the impedance can be mismatched at the other three signal levels that have not been calibrated. The three-point ZQ calibration [13] can match the impedance at +3, +1, and −1 output levels considering V DS variation, improving the linearity. When transmitting the −3 output level, however, the pull-down driver uses the driver codes obtained from the −1 output level.…”

Section: Design Considerationsmentioning

confidence: 99%

“…Electronics 2021, 10, x FOR PEER REVIEW 3 of 10 not been calibrated. The three-point ZQ calibration [13] can match the impedance at +3, +1, and −1 output levels considering VDS variation, improving the linearity. When transmitting the −3 output level, however, the pull-down driver uses the driver codes obtained from the −1 output level.…”

Section: Proposed Pam-4 Transmittermentioning

confidence: 99%

“…There have been PAM-4 transmitters that adopt a current-or voltage-mode driver, but PAM-4 transmitters using current-mode drivers [6,9,10] consume a lot of power. Therefore, PAM-4 transmitters using voltage-mode drivers, while improving the PAM-4 signal linearity, have been recently reported [5,[11][12][13]. However, in previous designs [5,11,12], the signal level distortion cannot be alleviated while matching the channel impedance, or the output impedance is calibrated based on only one output level; thus, impedance mismatch can occur at other signal levels.…”

Section: Introductionmentioning

confidence: 99%

“…However, in previous designs [5,11,12], the signal level distortion cannot be alleviated while matching the channel impedance, or the output impedance is calibrated based on only one output level; thus, impedance mismatch can occur at other signal levels. A PAM-4 transmitter with a three-point ZQ calibration [13] can match the impedance at +3, +1, and −1 levels considering the V DS variation but cannot match the impedance at −3 level with the channel impedance.…”

Section: Introductionmentioning

confidence: 99%

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An 18-Gb/s/pin Single-Ended PAM-4 Transmitter for Memory Interfaces with Adaptive Impedance Matching and Output Level Compensation

et al. 2021

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This paper presents a method for preventing output level distortion while matching the channel impedance in the single-ended PAM-4 transmitter for memory interfaces. ZQ codes for all four output signal levels were obtained through ZQ calibration and saved in the ZQ code table. The ZQ code generator then adaptively selected the appropriate codes depending on the data pattern and delivered them to the output driver; this can improve the level separation mismatch ratio (RLM) while matching the channel impedance. To validate the effectiveness of our approach, a prototype chip with an active area of 0.035 mm2 was fabricated in a 65 nm CMOS process. It achieved the energy efficiency of 3.09 pJ/bit/pin at 18 Gb/s/pin, and its RLM was 0.971 while matching the channel impedance.

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