A 0.5-5 GHz 0.3-mW 50% duty-cycle corrector in 65-nm CMOS

Zhang, Jiaqi; Meng, Xiangyu

doi:10.1109/tencon50793.2020.9293822

Cited by 2 publications

(3 citation statements)

References 12 publications

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Section: State-of-the-artmentioning

confidence: 99%

“…Generally speaking, analog architectures of DCC [7][8][9][10][11] usually take a feedback form, which can have higher resolution and operating frequency, but with a lengthy lock time. Digital architectures are usually a non-feedback type [10][11][12][13][14][15][16][17][18][19][20][21][22], and thus have a faster lock time. The high degree of circuit integration and the easy design of Digital architectures make the realization of this circuit more advantageous and developmental than the analog architectures.…”

Section: State-of-the-artmentioning

confidence: 99%

“…To control circuit triggering under high-frequency operation, the accuracy of the frequency, phase, and pulse width of the clock signal is important for circuit applications. However, the Phase Locked Loop (PLL) [1][2][3] or Delay Locked Loop (DLL) [4][5][6], can only correct the signal frequency and phase, so the Duty Cycle Corrector (DCC) [7][8][9][10][11][12][13][14][15][16][17][18][19][20] was developed to correct the output duty cycle. The duty cycle of a clock plays a very important role in many circuit operations.…”

Section: Introductionmentioning

confidence: 99%

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A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Kao

2021

Electronics

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This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm2, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.

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Section: State-of-the-artmentioning

confidence: 99%

Section: State-of-the-artmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Kao

2021

Electronics

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Design of duty cycle correction circuit using ASIC implementation for high speed communication

Siddesh,

Roopa,

Farzana

et al. 2023

JELE

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This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.

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A 0.5-5 GHz 0.3-mW 50% duty-cycle corrector in 65-nm CMOS

Cited by 2 publications

References 12 publications

A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Design of duty cycle correction circuit using ASIC implementation for high speed communication

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